Search - vhdl - CodeBus

[VHDL-FPGA-Verilog] VHDL

Description: VHDL 语言要素，可以帮助初学者，加深理解-VHDL
Platform: | Size: 28672 | Author: eason | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ldpc编码的vhdl的实现，一种802.13的方式-ldpc coding vhdl implementation, a 802.13 a way
Platform: | Size: 6144 | Author: lq | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

[VHDL-FPGA-Verilog] VHDL(LOCK)

Description: 数字密码锁的设计与实现一．实验目的 1. 学习VHDL的综合设计应用 2. 学习数字密码锁的设计二．实验内容设计一个数字密码锁，对其编译，仿真，下载。数字密码锁具体要求如下： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
Platform: | Size: 18432 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用vhdl语言实现了rsa算法功能，位宽可调-RSA
Platform: | Size: 7168 | Author: huyanzi | Hits:

[Mathimatics-Numerical algorithms] PID(VHDL)

Description: PID如何通过VHDL语言来实现，前来看看那这个文件吧-PID
Platform: | Size: 3072 | Author: wjz | Hits:

[Other] VHDL-Vending-machine

Description: 用VHDL设计自动售货机，能实现自动找零的功能。-Vending machines with VHDL design, auto-change function can be realized.
Platform: | Size: 540672 | Author: 毛毛 | Hits:

[Mathimatics-Numerical algorithms] 1024FFT(VHDL)

Description: 1024点的FFT源程序-1024 FFT VHDL
Platform: | Size: 203776 | Author: 倦怠怪兽 | Hits:

[VHDL-FPGA-Verilog] vhdl-pdelay

Description: programmable delay register (16-bit) in VHDL source code
Platform: | Size: 82944 | Author: bfuclin | Hits:

[Documents] VHDL-FIRfilter

Description: 利用vhdl实现fir低通滤波器的设计，并且使用了MATLAB，很好很强大。-VHDL MATLAB fir lowpass filter
Platform: | Size: 29696 | Author: 邵娜 | Hits:

[VHDL-FPGA-Verilog] DWT-VHDL

Description: 小波变换的VHDL代码，内带正变换逆变换的测试文件。-Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.
Platform: | Size: 18432 | Author: Janee | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
Platform: | Size: 2048 | Author: jacen | Hits:

[VHDL-FPGA-Verilog] IIR(vhdl)

Description: 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
Platform: | Size: 7168 | Author: sunnyhp | Hits:

[Other] TEXTI0-VHDL

Description: TEXTIO在VHDL中的仿真及应用，主要介绍了TEXTIOTEXTIO的基本原理，编写方法，测试方法- Simulation and application of the TEXTIO in the VHDL,
Platform: | Size: 176128 | Author: ma li | Hits:

[Other] The-vhdl-gold-reference-guide

Description: 是一个公司内的资料，介绍了vhdl的常用语法结构，并说明了一些平时很少注意到的问题，是对vhdl学习的很好补充-A company' s information on the vhdl common grammatical structure, and explains some of the problems usually little attention is a good supplement to learn vhdl
Platform: | Size: 182272 | Author: lideli5 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdl

[Software Engineering] vhdl-TAXI

[VHDL-FPGA-Verilog] VHDL(LOCK)

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] vhdl

[Mathimatics-Numerical algorithms] PID(VHDL)

[Other] VHDL-Vending-machine

[Mathimatics-Numerical algorithms] 1024FFT(VHDL)

[VHDL-FPGA-Verilog] vhdl-pdelay

[Documents] VHDL-FIRfilter

[VHDL-FPGA-Verilog] DWT-VHDL

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] IIR(vhdl)

[Other] TEXTI0-VHDL

[Other] The-vhdl-gold-reference-guide

[VHDL-FPGA-Verilog] fft(VHDL)

[Mathimatics-Numerical algorithms] FFT(VHDL)

[VHDL-FPGA-Verilog] DE2LCD_(VHDL)

[VHDL-FPGA-Verilog] vhdl

CodeBus www.codebus.net