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Description: verilog验证平台的使用
很不错 很详细 想具体-verilog verification platform is more like using a very good specific
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Size: 350208 |
Author: guoguo |
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Description: 一个基于Spartan3E板子的LCD接受的代码附带testbench-A board of LCD-based Spartan3E accepted code with testbench
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Size: 22528 |
Author: 小于 |
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Description: 这是一个perl程序
只需要在cmd中运行,参数为你的Verilog名字
功能是:半自动生成Verilog的testbench,提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------|
# |
#-----copyright(C) Xzmeng 2010-------------------------------|
# |
#Date:2010-12-18 21:55:48------------------------------------|
# |
#Run the pl followed with the verlog file name,such as aaa.v |
#Put the original verilog file(.v) in the current directory. |
#------------------------------------------------------------|
# |
#And you need to gurrantee that there is only one "input" or |
#"output" per line. |
# |
#------------------------------------------------------------|
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Size: 2048 |
Author: zishan |
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Description: TestBench for stop_watch in VHDL
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Size: 4096 |
Author: mmm |
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Description: Altera DDR SDRAM控制器完整Verilog代码包,包括Verilog源代码,Doc说明文档,仿真DDR芯片模型,仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
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Size: 752640 |
Author: 沈志 |
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Description: 是学习数字电路设计verilog语言,及Writing testbench的首先好书。-Writing testbench
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Size: 58368 |
Author: xy |
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Description: 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
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Size: 2048 |
Author: 王强 |
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Description: VHDL Dpram including clock divider, D4to7, Scan4Digit and of course TOP level as well as testbench info
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Size: 568320 |
Author: Brian |
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Description: 4-taps FIR VHDL code with testbench
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Size: 186368 |
Author: veerender |
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Description: verilog implementation of 16X4 fifo with testbench
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Size: 1024 |
Author: prateek |
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Description: 内含基于altera公司的FPGA芯片用modulesim仿真步骤,和详细实例,教会怎么使用modulesim仿真和编写testbench程序。-Altera FPGA-based embedded chip company with modulesim simulation steps, and detailed examples, how to use the church modulesim testbench simulation and preparation procedures.
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Size: 37552128 |
Author: guowei |
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Description: 一个简单的testbench示例,显示基本用法-testbench examples
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Size: 3072 |
Author: peter |
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Description: 用VHDL编写高效率testbench 中文-Efficient testbench written in VHDL Chinese
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Size: 324608 |
Author: Tom |
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Description: 用SystemVerilog编写testbench-SystemVerilog Testbench Constructs
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Size: 687104 |
Author: wang |
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Description: verilog testbench 编写入门,轻松教会编写测试代码-shell interpreter tutorial information, content, round and rich, from the basics
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Size: 57344 |
Author: 赵玉祥 |
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Description: 北大数字集成电路课件--15_Verilog-testbench的写法.ppt-Verilog-testbench .ppt
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Size: 73728 |
Author: yinxiupu |
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Description: 怎样写testbench , 仿真, modelsim, system verilog or verilog, 代码风格,行为级代码-how write testbench,do simulation, modelsim, system verilog or verilog , behaveral level code
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Size: 4096 |
Author: james |
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Description: 本文简单介绍了逻辑验证的入门知识—如何编写TESTBENCH进行逻辑测试-This paper briefly introduces the logic verification started- how to write TESTBENCH logic test
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Size: 61440 |
Author: zx |
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Description: 英文文章:testbench入门文档(xilinx的),ise开发软件-introduce of testbench
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Size: 197632 |
Author: yanyuwei |
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Description: 如何写好testbench,针对verilog语言-how to write testbench,aimed to verilog
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Size: 251904 |
Author: 郭良谦 |
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