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[VHDL-FPGA-Verilog] simplevhdl

Description: 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
Platform: | Size: 4096 | Author: yvonne | Hits:

[VHDL-FPGA-Verilog] shift_register_testbench

Description: 16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
Platform: | Size: 23552 | Author: yeqing | Hits:

[Other] debussy11

Description: This the famous hardware testbench technowlege word ,whici name is debussy ,it is helpfull for hardware design-This the famous tech hardware testbench nowlege word, whici name is debussy. it is helpful for hardware design
Platform: | Size: 647168 | Author: 王明 | Hits:

[VHDL-FPGA-Verilog] usb11_systemc

Description: USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
Platform: | Size: 193536 | Author: 里晓军 | Hits:

[VHDL-FPGA-Verilog] usb1_funct

Description: usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
Platform: | Size: 52224 | Author: liuzefu | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] ModelSim_TestBench_VHDL

Description: ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
Platform: | Size: 1024 | Author: 汤维 | Hits:

[File Format] SOC-normal-testbench-and-verification-methology.zi

Description: 属于论文的形式，介绍比较详细，在万方数据库中载的，有参考价值-papers belonging to the form, a more detailed briefing, in the popular database contains the reference value
Platform: | Size: 3712000 | Author: 王嘉 | Hits:

[Books] VHDL_TESTBENCH

Description: 怎样用VHDL写TESTBENCH.rar VHDL仿真-how to use VHDL to write VHDL simulation TESTBENCH.rar
Platform: | Size: 9594880 | Author: 高 | Hits:

[File Format] verilog_testbench_preliminary

Description: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Platform: | Size: 60416 | Author: 刘彦 | Hits:

[Linux-Unix] alu1

Description: alu,原程序及testbench,供初学者参考-alu, the original procedures and testbench and reference for beginners
Platform: | Size: 2048 | Author: dai hai bo | Hits:

[Linux-Unix] register19

Description: register,原程序及testbench,供初学者参考-register, the original procedures and testbench and reference for beginners
Platform: | Size: 3072 | Author: dai hai bo | Hits:

[Linux-Unix] timing19

Description: timing,原程序及testbench,供初学者参考-timing, the original procedures and testbench and reference for beginners
Platform: | Size: 1024 | Author: dai hai bo | Hits:

[VHDL-FPGA-Verilog] cfft

Description: 参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
Platform: | Size: 83968 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] RISCMCU

Description: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Platform: | Size: 594944 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] oc8051

Description: 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
Platform: | Size: 1226752 | Author: wutailiang | Hits:

[Other Embeded program] FIFO_v

Description: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Platform: | Size: 175104 | Author: wutailiang | Hits:

[Software Engineering] TestBench_writing

Description: testbench书写规范格式的ppt教程
Platform: | Size: 20480 | Author: ZHUOHUI LI | Hits:

[VHDL-FPGA-Verilog] systemverilog

Description: systemverilog是新出现的一种高级硬件描述和验证语言，这里给出了一些书和文章还有使用vmm方法开发testbench的例子
Platform: | Size: 1608704 | Author: 闫永志 | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:
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