Search - testbench

[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 56068 | Author: 地方 | Hits:

[Other resource] testbench

Description: 编写testbench的非常号的参考资料哦。
Platform: | Size: 244936 | Author: 文成 | Hits:

[Other resource] Testbench

Description: 单顶层结构化Testbench设计实例，适合硬件开发人员作为参考
Platform: | Size: 154933 | Author: xyq | Hits:

[Other resource] testbench

Description: 一片英语文章，详细描述了testbench的编写，尤其是assert和textio的用法，老外的文章就是不一样，看了之后让人茅塞顿开
Platform: | Size: 2094835 | Author: horse | Hits:

[Documents] how to write testbench

Description: 很好的，适合初学者Writing Efficient Testbenches
Platform: | Size: 196792 | Author: applehot@126.com | Hits:

[Documents] 逻辑验证与Testbench 编写

Description: 逻辑验证与Testbench 编写
Platform: | Size: 285391 | Author: bingxinhuier | Hits:

[VHDL-FPGA-Verilog] testbench模版

Description: testbench测试模版
Platform: | Size: 664 | Author: lmyapple | Hits:

[Program doc] testbench设计精华

Description: 介绍FPGA中testbench设计技巧
Platform: | Size: 56320 | Author: xiazgjay@163.com | Hits:

[VHDL-FPGA-Verilog] 比较器的测试矢量

Description: 一个很好的testbench的例子。
Platform: | Size: 3934 | Author: daxuerushui | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] flash接口控制_verilog

Description: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Platform: | Size: 870400 | Author: 李楠 | Hits:

[VHDL-FPGA-Verilog] vhdl实现alu的源代码

Description: VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
Platform: | Size: 1024 | Author: 飞扬 | Hits:

[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4096 | Author: 张雷 | Hits:

[VHDL-FPGA-Verilog] H16550_2[1].0V

Description: 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core.
Platform: | Size: 386048 | Author: 宋云成 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] wave_gen

Description: 波形发生器，带TESTBENCH，多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[Other] Art_of_writing_testbenches

Description: Art_of_writing_testbenches,学习写testbench的经典书籍-Art_of_writing_testbenches. Learning to write the classic books testbench
Platform: | Size: 78848 | Author: william | Hits:

[VHDL-FPGA-Verilog] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[VHDL-FPGA-Verilog] Modsim-AND-testbench

Description: 关于fpga中，测试平台testbench的技巧，及仿真软件MOSIDISIM-About fpga skills test platform testbench, and simulation software MOSIDISIM
Platform: | Size: 6334464 | Author: kehuan | Hits:

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[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

[Other resource] testbench

[Other resource] Testbench

[Other resource] testbench

[Documents] how to write testbench

[Documents] 逻辑验证与Testbench 编写

[VHDL-FPGA-Verilog] testbench模版

[Program doc] testbench设计精华

[VHDL-FPGA-Verilog] 比较器的测试矢量

[Crack Hack] rom_des

[VHDL-FPGA-Verilog] flash接口控制_verilog

[VHDL-FPGA-Verilog] vhdl实现alu的源代码

[Crack Hack] MD5(verilog)

[VHDL-FPGA-Verilog] H16550_2[1].0V

[VHDL-FPGA-Verilog] generic_fifo

[VHDL-FPGA-Verilog] wave_gen

[Other] Art_of_writing_testbenches

[VHDL-FPGA-Verilog] mdct.tar

[VHDL-FPGA-Verilog] ADPLL

[VHDL-FPGA-Verilog] Modsim-AND-testbench

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