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Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
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Size: 30494 |
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Size: 55801 |
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Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
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Size: 4806 |
Author: 张雷 |
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Description: 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core.
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Size: 386448 |
Author: 宋云成 |
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Description: 通用控件测试床，内含进度条、树形控件、list控件等常见控件，可以为C++新手上路者练习控件使用提供快捷方便的框架。-common control test bed consisting of the progress of the tree controls, list control and other common controls for the C Started practice controls used to provide fast and convenient framework.
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Size: 73110 |
Author: 瓦洛佳 |
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Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
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Size: 21078 |
Author: daiowen |
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Description: 波形发生器，带TESTBENCH，
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform -- the design makes use of the new shift opera tors available in the VHDL-93 std -- this design passes the Synplify synthesis check -- downloa d from : www.fpga.com.cn
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Size: 1184 |
Author: 罗兰 |
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Description: Art_of_writing_testbenches,学习写testbench的经典书籍-Art_of_writing_testbenches. Learning to write the classic books testbench
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Size: 79225 |
Author: william |
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Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。
The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation.
-This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
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Size: 1767014 |
Author: 陈朋 |
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Description: verilog ADPLL file with testbench.v
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Size: 25639 |
Author: 79979 |
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Description: 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。
希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3 -8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
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Size: 4034 |
Author: yvonne |
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Description: 16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
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Size: 24165 |
Author: yeqing |
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Description: This the famous hardware testbench technowlege word ,whici name is debussy ,it is helpfull for hardware design-This the famous tech hardware testbench nowlege word, whici name is debussy. it is helpful for hardware design
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Size: 647477 |
Author: 王明 |
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Description: USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
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Size: 193405 |
Author: 里晓军 |
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Description: usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
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Size: 52033 |
Author: liuzefu |
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Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
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Size: 2241 |
Author: seiji |
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Description: modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
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Size: 23041 |
Author: chengroc |
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Description: 基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)
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Size: 20480 |
Author: onewayxiang
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Description: testing testbench to device under test (dut)
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Size: 13312 |
Author: Brader
|
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Description: spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)
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Size: 5120 |
Author: CARL_2018 |
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