Search - sram - CodeBus

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] Protecting_FPGA

Description: How to protect your FPGA design (IP) on SRAM based FPGA s against copying.
Platform: | Size: 1542144 | Author: TR | Hits:

Description: verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
Platform: | Size: 21504 | Author: frankiecoco | Hits:

[Other] fpga-based-system-design-chapter3

Description: In this chapter we will study the basic structures of FPGAs, known as fabrics. We will start with a brief introduction to the structure of FPGA fabrics. However, there are several fundamentally different ways to build an FPGA. Therefore, we will discuss combinational logic and interconnect for the two major styles of FPGA: SRAM-based and antifuse-based. The features of I/O pins are fairly simi- lar among these two types of FPGAs, so we will discuss pins at the end of the chapter.
Platform: | Size: 388096 | Author: Frank | Hits:

[VHDL-FPGA-Verilog] SRAM_with_con

Description: 带有控制器的SRAM，提供一个地址选通脉冲ADS，一个读/写信号R_W,一个时钟信号和复位信号，包含了测试文件。-Controller with the SRAM, providing a strobe pulse Address ADS, a read/write signal R_W, a clock signal and reset signal, including the test documents.
Platform: | Size: 3072 | Author: isaac | Hits:

[VHDL-FPGA-Verilog] SRAM_Controller

Description: SRAM controller用于控制sram -SRAM controller
Platform: | Size: 320512 | Author: liufl | Hits:

[VHDL-FPGA-Verilog] cy7c1371c_vhdl_10

Description: cy7c1371c ZBT SRAM 的仿真模型，VHDL编写。-the simulate model of cy7c1371c,VHDL language.
Platform: | Size: 7168 | Author: Tangyao | Hits:

[VHDL-FPGA-Verilog] SRAM_controller

Description: asynchronus SRAM controller
Platform: | Size: 7168 | Author: Vijay Baraiya | Hits:

[VHDL-FPGA-Verilog] de2_lcm_ccd_sram

Description: 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
Platform: | Size: 918528 | Author: ningning | Hits:

[VHDL-FPGA-Verilog] SRAM_Controller

Description: Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Platform: | Size: 324608 | Author: vicky | Hits:

[Documents] SRAM_2006

Description: PPT of the SRAM, new development
Platform: | Size: 467968 | Author: arthur | Hits:

[Windows Develop] IS61WV51216

Description: iss simulation model for 512KX16 SRAM
Platform: | Size: 3072 | Author: deep | Hits:

[VHDL-FPGA-Verilog] sram_test

Description: fpga读写SRAM的VERILOG 代码-the verilog code of fpga write/read sram
Platform: | Size: 1024 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

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[Other] interleaver

[VHDL-FPGA-Verilog] Protecting_FPGA

[VHDL-FPGA-Verilog] PWM

[Other] fpga-based-system-design-chapter3

[VHDL-FPGA-Verilog] SRAM_with_con

[VHDL-FPGA-Verilog] SRAM_Controller

[VHDL-FPGA-Verilog] cy7c1371c_vhdl_10

[VHDL-FPGA-Verilog] SRAM_controller

[VHDL-FPGA-Verilog] de2_lcm_ccd_sram

[VHDL-FPGA-Verilog] SRAM_Controller

[Documents] SRAM_2006

[Windows Develop] IS61WV51216

[VHDL-FPGA-Verilog] sram_test

[VHDL-FPGA-Verilog] yuyincaiji

[VHDL-FPGA-Verilog] SSRAM_CONTROLLER

[Other Embeded program] STC_2uart-sram

[Other] code_20-08-09

[VHDL-FPGA-Verilog] FPGA2SRAM

[VHDL-FPGA-Verilog] 512

[VHDL-FPGA-Verilog] rams

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