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[WEB CodeICR-SRAM

Description: 基于SRAM的可重配置电路-SRAM-based reconfigurable circuit
Platform: | Size: 17690 | Author: 王自强 | Hits:

[Other resourcesram

Description: sram 读写小程序,用verilog编写的,请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1206 | Author: kevin | Hits:

[ApplicationsZBT SRAM

Description: 用verilog HDL写的操作SRAM的源码-with Verilog HDL write operation SRAM FOSS
Platform: | Size: 6435 | Author: 刘波 | Hits:

[Other resourceSRAM

Description: 是一个基于VHDL的SRAM程序,很有代表意义,下下吧
Platform: | Size: 3773 | Author: 张俊 | Hits:

[Other resourceSRAM

Description: 静态随机存储器(SRAM)设计VHDL代码,已经生成的了
Platform: | Size: 345796 | Author: 陆见风 | Hits:

[Other resourceSRAM

Description: SRAM编译过的源代码 强烈推荐
Platform: | Size: 3137 | Author: JP | Hits:

[Other resourcesram+lcd

Description: 用vhdl格式写的sram源代码,把扩展名txt改为.v即可
Platform: | Size: 1979 | Author: 郭艳红 | Hits:

[Other resourcesram

Description: FPGA向SRAM中写入数据(VHDL编程),包含通用fifo,sram等
Platform: | Size: 270755 | Author: 王刚 | Hits:

[Other resourceSRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建,图像存储器就必须不断地写入数据,同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求,可以在采集系统中设置2片容量一样的SRAM,通过乒乓读写机制来管理。任何时刻,只能有1片SRAM处于写状态,同时也只有1片SRAM处于读状态。工作期间,2片SRAM都处于读写状态轮流转换的过程,转换的过程相同,但是状态错开,从而保证数据能连续地写人和读出祯存.
Platform: | Size: 1214 | Author: smj1980 | Hits:

[Other resourceSRAM

Description: STM32F103VBT6 实现SRAM
Platform: | Size: 676176 | Author: yuan | Hits:

[Driver DevelopSRAM

Description: 这是一个sram接口驱动程序,能够驱动256kbx16bit的sram
Platform: | Size: 11459 | Author: chenyizhong | Hits:

[VHDL-FPGA-Verilogsram控制器

Description: 基于nios ii 的sram控制器
Platform: | Size: 218458 | Author: jinsam | Hits:

[SourceCode调试STM32外部SRAM

Description: IAR编译环境下的STM32外部SRAM调试程序~
Platform: | Size: 858489 | Author: muhu_lee@163.com | Hits:

[ApplicationsSRAM

Description: 内存的介绍,从最早的内存开始讲起的,直到现在的 DDRII哦-memory, the memory from the earliest start of the 1960s and now the DDRII oh
Platform: | Size: 712704 | Author: | Hits:

[DocumentsICR-SRAM

Description: 基于SRAM的可重配置电路-SRAM-based reconfigurable circuit
Platform: | Size: 17408 | Author: 王自强 | Hits:

[SCM3300iap

Description: 尽量朝“单片”方向设计硬件系统。系统器件越多,器件之间相互干扰也越强,功耗也增大,也不可避免地降低了系统的稳定性。随着单片机片内集成的功能越来越强,真正的片上系统SoC已经可以实现,如ST公司新近推出的μPSD32××系列产品在一块芯片上集成了80C32核、大容量FLASH存储器、SRAM、A/D、I/O、两个串口、看门狗、上电复位电路等等。 -North Korea as the "single-chip" design direction of the hardware system. System devices more mutual interference between devices are more strong, power consumption is increased, it will inevitably reduce system stability. With MCU with on-chip integration of more powerful, the real system-on-chip SoC can achieve, such as ST's new PSD32 x x in a series chip integrates exertion nuclear, large-capacity flash memory, SRAM, A/D, I/O, 2 serial port, watchdog, the power-on reset circuit and so on.
Platform: | Size: 535552 | Author: 东东 | Hits:

[SCMAN06SW

Description: 外部SRAM与C8051F000接口 Copyright (C) 2000 CYGNAL INTEGRATED PRODUCTS, INC. All rights reserved. FILE NAME : Sram.ASM TARGET MCU : C8051F000 DESCRIPTION : External Sram read/write verification routine for IDT 71V124SA.-external SRAM interface with the C8051F000 Copyright (C) 2000 CYGNAL INTEGRATED PRODUCTS, INC. All rights reserved. FILE NAME : MCU Sram.ASM TARGET : C8051F000 DESCRIPTION : External Sram read/write verification routine for IDT 71V124SA.
Platform: | Size: 2048 | Author: | Hits:

[Other51汇编程序1ASM

Description: 本程序用于测试实时时钟模块SD2000的SRAM存储器D/E系列, 程序功能如下: 1. 关闭/INT1及/INT2的中断输出 2. 初始化时间(写时间数据) 3. 在BREAKPOINT1设断点时,依次读时间-写SRAM数据-读SRAM数据循环 4. 全速执行时,LED四位分别显示小时和分钟的值-procedures used to test the real-time clock module SD2000 SRAM memory D/E Series, procedures following functions : 1. Closed/INT1 and/INT2 the interruption of output 2. Initialization time (the time to write data) 3. Located in BREAKPOINT1 breakpoint, followed by time for-write SRAM data-reading cycle of four data SRAM. full speed of implementation, respectively, four LED display hours and minutes values
Platform: | Size: 4096 | Author: 小顽童 | Hits:

[Othersdram32

Description: sram 存储器控制程序很完整,值得认真研究,很有帮组-SRAM memory control program is very complete, worthy of serious study, is to help groups
Platform: | Size: 23552 | Author: 许曲 | Hits:

[VHDL-FPGA-Veriloghanbaosram

Description: 德国汉堡大学的SRAM测试代码,使用VHDL编写,供大家参考-University of Hamburg, Germany, SRAM test code, the use of VHDL, for your reference
Platform: | Size: 6144 | Author: 汪涌 | Hits:
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