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[VHDL-FPGA-Verilog] sw_leds

Description: 精简指令cpu设计，外扩电路设计，led开发板驱动-wb_sw_leds，opencore，risc cpu design。
Platform: | Size: 1024 | Author: 浮萍 | Hits:

[Crack Hack] aes_pipe_latest.tar

Description: AES Pipe RTL Code, Support 128/192/256bits key Come from OpenCore.-AES Pipe RTL code
Platform: | Size: 186368 | Author: Jassen | Hits:

[android] 48564

Description: opencore官方文档中文版，精选android项目书籍，很好有参考资料。-OpenCORE official documents Chinese version, select Android project books, very good reference material.
Platform: | Size: 914432 | Author: 南煎丸子 | Hits:

[android] 706567

Description: Android的多媒体框架OpenCore介绍，精选android项目书籍，很好有参考资料。-OpenCore multimedia framework Android, select Android project books, very good reference material.
Platform: | Size: 448512 | Author: 紫菜蛋花 | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。 相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Platform: | Size: 12288 | Author: 程浩武 | Hits:

[VHDL-FPGA-Verilog] CAN_VHD.ZIP

Description: CAN VHDL Controller Area Network en languge VHDL CAN VHDL Opencore
Platform: | Size: 51200 | Author: Mengkoung | Hits:

[Software Engineering] RosettaPdatasheetPV0_1

Description: Project Name is ROSETTA Configurable Dot Matrix Display Controller.I prefered from opencore.org
Platform: | Size: 754688 | Author: thuanbk | Hits:

[Other] fpga_noc.tar

Description: fpga实现的片上网络代码，代码很齐全，有文档，是从opencore上下载下来的-fpga realize on-chip network code, the code is complete, the document is downloaded the opencore down
Platform: | Size: 1664000 | Author: 黄锦辉 | Hits:

[Other] fpga_NOC_mpsoc

Description: fpga实现的片上网络代码，代码很齐全，有文档，是从opencore上下载下来的-fpga realize on-chip network code, the code is complete, the document is downloaded the opencore down
Platform: | Size: 1842176 | Author: 黄锦辉 | Hits:

[Software Engineering] opencore-amr-iOS-master

Description: OPEN Core AMR Compilation For iPHone
Platform: | Size: 1422336 | Author: Arslan | Hits:

[VHDL-FPGA-Verilog] ethernet

Description: opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
Platform: | Size: 1017856 | Author: TSH | Hits:

[Other] m16c5x_latest.tar

Description: PIC的8位单片机的源码，芯片16CX的源代码，摘自opencore的源代码，真实可用的- This project demonstrates the use of a PIC16C5x-compatible core as an FPGA- based processor. It implements the 12-bit instruction set, the timer 0 module, the pre-scaler, and the watchdog timer.
Platform: | Size: 171008 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] CANBus_design

Description: CAN总线代码，除了opencore上的ip核之外，主要是原创的配置CAN核和数据采集传输部分-CAN bus code, in addition to the ip nuclear opencore on the original configuration of CAN main nuclear data acquisition and transmission section
Platform: | Size: 114688 | Author: 李阔 | Hits:

[OS program] conggstelevator

Description: opencore-amr-0,1,3 windows版本的,a库文件和头文件,使用minGW编译-Opencore amr- 0,1,3 versions of Windows, a library and header files, using minGW compiler
Platform: | Size: 445440 | Author: genexic | Hits:

[source in ebook] forwarding

Description: opencore-amr-0,1,3 windows版本的,a库文件和头文件,使用minGW编译-Opencore amr- 0,1,3 versions of Windows, a library and header files, using minGW compiler
Platform: | Size: 445440 | Author: PICKaky_793657 | Hits:

[USB develop] OpenCoreUSB2IP

Description: OpenCore 的 USB2.0 IP-OpenCore 的 USB2.0 IP全套资料，包括源代码、设计文档等
Platform: | Size: 196608 | Author: 徐兰天 | Hits:

[VHDL-FPGA-Verilog] OpenCores-Amber

Description: 木马硬件在OpenCore Amber ARM Core中实现-Trojan Hardware implemented in the OpenCores Amber ARM Core
Platform: | Size: 8462336 | Author: 骆扬 | Hits:

[Other] compieer_header

Description: opencore-amr-0,1,3 windows版本的,a库文件和头文件,使用minGW编译-Opencore amr- 0,1,3 versions of Windows, a library and header files, using minGW compiler
Platform: | Size: 445440 | Author: LHIU$4791 | Hits:

[Other] alquire

Description: Opencore amr - 0,1,3 versions of Windows, a library and header files, using minGW compiler
Platform: | Size: 444416 | Author: zsederiga | Hits:

[ComboBox] linw

Description: opencore-amr-0,1,3 windows版本的,a库文件和头文件,使用minGW编译()
Platform: | Size: 444416 | Author: Thgresj | Hits:
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