Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: CANBus_design Download
 Description: CAN bus code, in addition to the ip nuclear opencore on the original configuration of CAN main nuclear data acquisition and transmission section
 Downloaders recently: [More information of uploader 李阔]
 To Search:
File list (Check if you may need any files):
 

CAN_test.v
CAN_Tran_top.v
data_port.v
data_receive.v
init.v
state_mux.v
trans.v
uart_rx.v
uart_top.v
uart_tx.v
wr_buf.v
CAN_IP\can_acf.v
......\can_acf.v.bak
......\can_bsp.v
......\can_bsp.v.bak
......\can_btl.v
......\can_btl.v.bak
......\CAN_Controller.pti_db_list.ddb
......\CAN_Controller.tis_db_list.ddb
......\can_crc.v
......\can_defines.v
......\can_fifo.v
......\can_fifo.v.bak
......\can_ibo.v
......\CAN_ISSP_Test.pti_db_list.ddb
......\CAN_ISSP_Test.tis_db_list.ddb
......\can_register.v
......\can_registers.v
......\can_registers.v.bak
......\can_register_asyn.v
......\can_register_asyn_syn.v
......\can_register_syn.v
......\can_testbench.v
......\can_testbench.v.bak
......\can_testbench_defines.v
......\can_top.v
......\can_top.v.bak
......\timescale.v
baudrate_set.v
CAN_Rec_top.v
....IP\output_files
CAN_IP
    

CodeBus www.codebus.net