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Description: 100M-MAC-IPcore（从OPENCORE下载)；-100M of the MAC
Platform: |
Size: 2023424 |
Author: hlj |
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Description: 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
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Size: 683008 |
Author: Joe |
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Description: opencore里面的 i2s的VHDL硬件源代码，-The VHDL hardware i2s source code,
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Size: 245760 |
Author: 陈达燕 |
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Description: opencore ,csa 的vhdl硬件源代码，-opencore, csa of vhdl hardware, source code,
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Size: 46080 |
Author: 赵文军 |
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Description: 最流行的OPENCORE的学习资料，很全面的介绍了OPENCORE的结构-The most popular OPENCORE learning materials, it is a comprehensive introduction to the structure of the OPENCORE
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Size: 164864 |
Author: hcq |
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Description: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Platform: |
Size: 45056 |
Author: davi_insist |
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Description: ffmpeg for android library
anroid手机上的一个音视频编解码库-ffmpeg for android library
Platform: |
Size: 779264 |
Author: dmyss |
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Description: IT51, re-vised opencore T51 in Verilog.
Platform: |
Size: 36864 |
Author: Bryan Lin |
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Description: my_atan_cordic.xco - Core parameter file
my_atan_cordic.vho - Core VHDL instantiation template
my_atan_cordic.vhd - Core VHDL simulation file (only for simulation)
my_atan_cordic.edn - Core EIDF netlist (only for implementation)
x_in_cos.dat - input data for the simulation (only for simulation)
y_in_cos.dat - input data for the simulation (only for simulation)
cordic_functional.do - ModelSim do file for functional simulation
cordic_timing.do - ModelSim do file for timing simulation
design_top.ucf - contrsaints file (only for implementation)
design_top.vhd - VHDL toplevel
design_top_tb.vhd - VHDL testbench
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Size: 118784 |
Author: d |
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Description: 这个是关于在opencore下集成其他的core的集成向导，很好。-This is about the integration of the other under the opencore core of the integrated wizard, very good.
Platform: |
Size: 216064 |
Author: chenxiaoxiao |
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Description: 三星提供 的 android cupcake 下多媒体播放软件 当平台支持avc 264硬解码时 可直接调opencore中硬解码组件-Samsung' s android cupcake when the next platform media player software to support hardware decoding avc 264 can be directly transferred opencore components in the hard decoding
Platform: |
Size: 250880 |
Author: seven |
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Description: android 播放本地以及网络流（rtsp）视音频文件的上层java程序。主要供初学者理解mediaplayer的使用方法，以及调试下层opencore。在android2.1及以上使用。-android Play local and network flow (rtsp) on top of video and audio files java program. Mediaplayer for beginners to understand the main use of methods, and debugging the lower opencore. In android2.1 and over use.
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Size: 47104 |
Author: 张伟 |
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Description: 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
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Size: 224256 |
Author: robin |
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Description: 机器人相关资料，采用vhdl语言编程设计，来源opencore,许多例子-Robot-related information, using vhdl programming language design, source opencore, many examples
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Size: 249856 |
Author: asfk |
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Description: 串口通信后处理程序，可以对收到，到的数据进行处理，来源opencore-After serial communication process, can be received, the data processing, source opencore
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Size: 564224 |
Author: asfk |
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Description: Android opencore asf文件格式解析-Android opencore asf parser
Platform: |
Size: 81920 |
Author: allen |
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Description: amr转码用，ios语音开发用到，不需要自动忽略-amr transcoding with ios voice development used, and do not need to automatically ignore
Platform: |
Size: 1290240 |
Author: csz2136 |
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Description: opencore can bus verilog design file-opencore can bus verilog design file
Platform: |
Size: 93184 |
Author: zhixiaowen |
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Description: wb_switch，cpu设计，精简指令cup设计-wb_switch，opencore，risc cpu design。
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Size: 36864 |
Author: 浮萍 |
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Description: wb_switch，opencore，精简指令cpu设计-wb_switch，opencore，risc cpu design。
Platform: |
Size: 2048 |
Author: 浮萍 |
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