Search - opencore

[ASP] ata

Description: 用wincvs从opencore网站上下载下来的IPCore,可以直接使用
Platform: | Size: 5367 | Author: liuhongjie | Hits:

[Other resource] H.264_VHDL

Description: VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。
Platform: | Size: 3351222 | Author: Jimmy Huang | Hits:

[VHDL-FPGA-Verilog] video_from_opencore

Description: 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?
Platform: | Size: 152576 | Author: 12 | Hits:

Description: ARM7TM core源码，此码来自于opencore组织，此组织免费提供一些IP core，都是一些老外写的。-ARM7TM core source, the code from opencore organizations, this organization provided free IP core, are written by foreigners.
Platform: | Size: 70656 | Author: | Hits:

[Audio program] ts_126073v060000p0

Description: GSM AMR-NB speech codec R98 Version 7.6.0 December 12, 2001 R99 Version 3.3.0 REL-4 Version 4.1.0 REL-5 version 5.3.0 REL-6 version 6.0.0 -GSM AMR-NB speech codec R98 Version 7.6.0 D ecember 12, 2001's R99 Version 3.3.0 REL-4 Version 4.1.0 REL- 5 version 5.3.0 REL-6 version 6
Platform: | Size: 832512 | Author: 朱平 | Hits:

[VHDL-FPGA-Verilog] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[Other] i2c_master

Description: Avalon I2C master. Ready to use with SOPC.
Platform: | Size: 23552 | Author: Davide Merlani | Hits:

[Software Engineering] Wishbone_from_opencores

Description: 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。-This is collected in OPENCORE Wishbone bus and guide the development of note, with the electronic design of a large number of open source IP applications, wishbone bus is also becoming increasingly popular.
Platform: | Size: 836608 | Author: 刘庆强 | Hits:

[VHDL-FPGA-Verilog] BiDirectionalCell

Description: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] ControlCell

Description: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] InputCell

Description: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] OutputCell

Description: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Platform: | Size: 1024 | Author: hegs | Hits:

[SCSI-ASPI] ata

Description: 用wincvs从opencore网站上下载下来的IPCore,可以直接使用-Using WinCVS from opencore website down IPCore, can be directly used
Platform: | Size: 5120 | Author: liuhongjie | Hits:

[OS Develop] FIFO

Description: 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
Platform: | Size: 18432 | Author: zhangjing | Hits:

[SCM] RS485

Description: 用VERILOG语言写的RS485通信程序,经调试可以直接使用-Verilog language used to write the RS485 communication program, the debugger can be used directly
Platform: | Size: 653312 | Author: 李俭 | Hits:

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[ASP] ata

[Other resource] H.264_VHDL

[VHDL-FPGA-Verilog] video_from_opencore

[VHDL-FPGA-Verilog] sARM7TM

[Audio program] ts_126073v060000p0

[VHDL-FPGA-Verilog] mdct.tar

[Other] i2c_master

[Software Engineering] Wishbone_from_opencores

[VHDL-FPGA-Verilog] BiDirectionalCell

[VHDL-FPGA-Verilog] ControlCell

[VHDL-FPGA-Verilog] InputCell

[VHDL-FPGA-Verilog] OutputCell

[SCSI-ASPI] ata

[OS Develop] FIFO

[SCM] RS485

[VHDL-FPGA-Verilog] PCI

[Other Embeded program] i2c

[Embeded-SCM Develop] ahb2wishbone_latest.tar

[ARM-PowerPC-ColdFire-MIPS] arm7-verilog

[Embeded-SCM Develop] spi_boot_latest[1].tar

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