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[Other resourceDDS数字信号发生器

Description: DDS数字信号发生器,采用AD9835DDS 专用芯片 输出范围1K--10MHZ 采用X25045作看门狗及数据存储器,用于设置各项参数的存储 内含电路图, 源程序 及一些相关资料-DDS digital signal generator, using AD9835DDS ASIC output range 1K -- Knoxville watchdog for the use of X25045 and data memory, used to set various parameters of storage containing circuit, the source and related information
Platform: | Size: 2219855 | Author: 董庆 | Hits:

[Communication-MobileDDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145605 | Author: 李敏 | Hits:

[Other resourcedds-design

Description: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
Platform: | Size: 849 | Author: 魏杰 | Hits:

[CommunicationProject1-DDS

Description: 直接频率和成DDS,可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8611 | Author: lf | Hits:

[OtherDDS

Description: 用FPGA实现的DDS,用法简单,波形稳定(DDS is implemented using FPGA)
Platform: | Size: 1977344 | Author: 刘奔 | Hits:

[VHDL-FPGA-VerilogDDS

Description: 基于FPGA的DDS正弦信号设计,文件中有源代码(Design of DDS based on FPGA)
Platform: | Size: 51200 | Author: hdu | Hits:

[VHDL-FPGA-Verilog四通道DDS信号发生器

Description: 四通道DDS信号发生器,很好用的代码,大家一起分享(Four-channel DDS signal generator)
Platform: | Size: 6792192 | Author: sauno | Hits:

[VHDL-FPGA-VerilogDDS

Description: 用verilog语言,在fpga上实现dds信号发生器,并在vga上显示出来(Verilog realizes DDS Signal Generator)
Platform: | Size: 39298048 | Author: 灵风轩允 | Hits:

[OtherDDS

Description: 描述了verilog实现的DDS信号发生器,可以经过FPGA验证,包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证,可以实现信号发生器的基本功能。希望大家珍惜,并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be verified by the Altera EDA tool, you can achieve the basic functions of the signal generator. I hope you will cherish and study well.)
Platform: | Size: 104448 | Author: 西门电工 | Hits:

[Embeded-SCM Develop实验13-DDS技术-键盘反转法-2

Description: 用MSP430外加矩阵键盘实现DDS正弦波,方波的输出(Using MSP430 plus matrix keyboard to achieve DDS sine wave, Fang Bo output)
Platform: | Size: 50176 | Author: 十月的记忆 | Hits:

[VHDL-FPGA-VerilogDDS

Description: 可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)
Platform: | Size: 5120 | Author: preman | Hits:

[Database systemDDS AD9835

Description: DDS介绍了一种DDS专用芯片AD9835,并利用该芯片设计了一种高精度频率信号发生器,讨论了DDS芯片的基本原理、应用及其与计算机、单片机的接口。(A special chip AD9835 for DDS is introduced, and a high precision frequency signal generator is designed with this chip. The basic principle and application of DDS chip and its interface with computer and MCU are discussed.)
Platform: | Size: 148480 | Author: Qianna | Hits:

[VHDL-FPGA-VerilogDDS

Description: DDS直接数字合成器,里面包含相关的顶层文件,加法器,D触发器,mif文件(DDS direct digital synthesizer, which contains related top layer files, adder, D trigger, MIF file)
Platform: | Size: 4638720 | Author: Alexander_凡 | Hits:

[VHDL-FPGA-VerilogDDS的VERILOG原代码

Description: 实现了DDS的verilog源代码,可以使用(ajhsjdhjkshfjhfsjkjksa)
Platform: | Size: 3072 | Author: 骑单车追飞机 | Hits:

[VHDL-FPGA-VerilogDDS -changed

Description: DDS技术实现波形产生代码,可以编译下载学习使用!(DDS generate diagram program)
Platform: | Size: 4986880 | Author: shilj | Hits:

[SCMDDS v1.0

Description: 硬件平台:红牛stm32F103ZE开发板,DDS模块:AD9910 软件版本:Keil 4 固件库版本:v3.5 完成功能: (1)产生频率范围:1Hz - 400MHz 的正弦波(按键触发(F = 100KHz,Vpp:500mV):开发板上 WAKEUP 按键) (2)产生幅度范围:1mV - 650mV 的正弦波(初始化后:F = 100Hz,Vpp:100mV) (3)产生上下限频率、频率步进(单位:Hz)、步进时间间隔(单位:us;输入范围:1-262us)可调的扫频波(按键触发(Fmin = 1KHz,Fmax = 100KHz,频率步进:10Hz,步进时间间隔:240us,Vpp:500mV):开发板上 USER1 按键)(Hardware platform: Red Bull stm32F103ZE development board, DDS module: AD9910. Software version: Keil 4 Firmware library version: v3.5 Complete function: (1) produce frequency range: 1Hz - 400MHz sine wave (keystroke trigger (F = 100KHz, Vpp:500mV): WAKEUP button on development board). (2) the amplitude range is 1mV - 650mV sine wave (initialization: F = 100Hz, Vpp:100mV). (3) generation of upper and lower frequency, frequency step (unit: Hz), step time interval (unit: US; input range: 1-262us) adjustable sweep wave (key trigger (Fmin = 1KHz, Fmax = 100KHz, frequency step: 10Hz, step time interval: 240us, Vpp:500mV): developing the USER1 button on board))
Platform: | Size: 308224 | Author: NLQ | Hits:

[SCMDDS v2.0

Description: 硬件平台:红牛stm32F103ZE开发板,DDS模块:AD9910 软件版本:Keil 4 固件库版本:3.5 已完成功能: (1)产生频率范围:1Hz - 400MHz 的正弦波(按键触发:开发板上 WAKEUP 按键) (2)产生幅度范围:1mV - 650mV 的正弦波(初始化后为:500mV) (3)产生上下限频率、频率步进(单位:Hz)、步进时间间隔(单位:us;输入范围:1-262us)可调的扫频波(按键触发:开发板上 USER1 按键) (4)利用 RAM 调制模式产生方波:采样时间间隔为 4*(1~65536)ns(按键触发:开发板上 USER2 按键) (5)理论上可用 RAM 调制模式产生任意波形。(Hardware platform: Red Bull stm32F103ZE development board, DDS module: AD9910. Software version: Keil 4 Firmware library version: 3.5 Completed functions: (1) produce frequency range: 1Hz - 400MHz sine wave (keypad trigger: WAKEUP button on development board). (2) the amplitude range is 1mV - 650mV sine wave (initialization: 500mV). (3) generation of upper and lower frequency, frequency step (unit: Hz), step time interval (unit: US; input range: 1-262us) adjustable sweep wave (key trigger: USER1 button on the development board) (4) use RAM modulation mode to generate Fang Bo: the sampling interval is 4* (1~65536) ns (button trigger: USER2 button on the development board). (5) theoretically, arbitrary waveform can be generated by RAM modulation mode.)
Platform: | Size: 310272 | Author: NLQ | Hits:

[VHDL-FPGA-Verilogdds

Description: dds算法,调用xilinx IP ,ise(DDS algorithm, call Xilinx IP, ISE)
Platform: | Size: 5728256 | Author: 阿士大夫 | Hits:

[VHDL-FPGA-VerilogDDS

Description: 基于FPGA的DDS信号发生器,可产生频率可调的正弦波(DDS signal generator based on FPGA)
Platform: | Size: 3398656 | Author: cdy | Hits:

[Embeded-SCM DevelopFREQ-DDS

Description: STM8 ad9833 ad603 12864 DDS信号源 完整版程序 含上位机接口程序
Platform: | Size: 222680 | Author: 2095701351@qq.com | Hits:
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