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[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
Platform: | Size: 949248 | Author: 郭强 | Hits:

Description: 基于vhdl的dds信号发生器，可产生方波，三角波，正弦波，幅度，频率，相位可调-The signal generator based on VHDL DDS, can produce square wave, triangle wave, sine wave, amplitude, frequency, phase can be adjusted
Platform: | Size: 1628160 | Author: | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
Platform: | Size: 5120 | Author: 张君 | Hits:

[VHDL-FPGA-Verilog] quartus-dds

Description: quartus环境下利用原理图方式实现DDS的图文教程，主要掌握原理图输入，quartus仿真功能-quartus environment using the schematic approach of DDS graphic tutorial, the main control schematic, quartus simulation
Platform: | Size: 516096 | Author: ranshaoqiang | Hits:

[SCM] DDS-9850

Description: 基于9850和AVR单片机的DDS波形合成很简单的教程以及各种论文-Based on 9850 and AVR microcontroller DDS waveform synthesis is very simple tutorial and various papers
Platform: | Size: 882688 | Author: 孙帅 | Hits:

[ARM-PowerPC-ColdFire-MIPS] DDS

Description: 基于STM32库函数的DDS函数输出器.绝对可以运行试验-Base on the ADS9852 and Stm32-----DDS.
Platform: | Size: 535552 | Author: 郭文 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
Platform: | Size: 6281216 | Author: 王凡 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
Platform: | Size: 1288192 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] DDS-in-Verilog

Description: Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
Platform: | Size: 464896 | Author: haby | Hits:

[VHDL-FPGA-Verilog] DDS

Description: verilogHDL语言编写，带测试文件DDS波形发生器.-DDS waveform generator, verilogHDL language, with the test file
Platform: | Size: 1282048 | Author: 周舟 | Hits:

[SCM] AD9834-DDS-C51

Description: 基于AD9834 DDS芯片的驱动程序实现宽带宽波形输出-Based on the driver AD9834 DDS chip to achieve wide bandwidth waveform output
Platform: | Size: 26624 | Author: 周亚彬 | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件，-verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
Platform: | Size: 3013632 | Author: 颜小超 | Hits:

[matlab] DDS

Description: DDS功能仿真，用MATLAB仿真DDS功能，通过控制频率控制字实现不同频率正弦波的输出。-DDS functional simulation, using MATLAB simulation DDS functions, by controlling the frequency control word different frequency sine wave output.
Platform: | Size: 1024 | Author: 李冰 | Hits:

[VHDL-FPGA-Verilog] Verilog-dds

Description: 用Verilog实现的DDS，直接频率合成器，相位可调。-Verilog DDS generator
Platform: | Size: 1184768 | Author: fu | Hits:

[matlab] dds

Description: DDS信号的产生程序，以及DDS相关文章，综合报告。-DDS signal generation procedures and the DDS articles, comprehensive reports.
Platform: | Size: 669696 | Author: huihui | Hits:

[Other] DDS

Description: 基于dds原理产生频率信号,输入一个基准信号即可产生任意高于其频率的信号(Generation of frequency signals based on the DDS principle)
Platform: | Size: 64512 | Author: 程序猿就是我 | Hits:

[Other] DDS

Description: DDS的字长决定了正弦/余弦基准信号样点的个数和所产生频率信号的量化精度。最小频率间隔决定了DDS所能产生信号的最小频率。DDS所产生信号的频率为最小频率间隔的整数倍。(The word length of the DDS determines the number of sample points of the sine / cosine reference signal and the quantization accuracy of the generated frequency signals. The minimum frequency interval determines the minimum frequency that the DDS can generate. The frequency of the signal generated by the DDS is an integer multiple of the minimum frequency interval.)
Platform: | Size: 2048 | Author: YkY101 | Hits:

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[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] quartus-dds

[SCM] DDS-9850

[ARM-PowerPC-ColdFire-MIPS] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS-in-Verilog

[VHDL-FPGA-Verilog] DDS

[SCM] AD9834-DDS-C51

[VHDL-FPGA-Verilog] dds

[matlab] DDS

[VHDL-FPGA-Verilog] Verilog-dds

[matlab] dds

[Other] DDS

[Other] DDS

[hardware design] DDS 信号模块AD9850模块资料

[VHDL-FPGA-Verilog] dds(1)

[VHDL-FPGA-Verilog] DDS波形发生器

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