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[File Format] JESD79-2F

Description: ddr2 标准，详细描述了DDR2 的时序要求，详见http://www.jedec.org/-ddr2 spec for details :http://www.jedec.org/
Platform: | Size: 1802240 | Author: bluefeifei | Hits:

[VHDL-FPGA-Verilog] PCIeDDR2add

Description: PCIE-DDR2-双通道ADDA板主要用于AD数据的记录与回放。该板主要使用Xilinx公司的Virtex5 FPGA，通过PCIE IP核与主机通讯，存储系统包括DDR2 SDRAM和FLASH，为各种软件无线电技术的应用提供了一个非常强大的单插槽收发器解决方案。-PCIE-DDR2 dual-channel ADDA board is mainly used for the AD data recording and playback. The board Virtex5 the FPGA using Xilinx PCIE IP core and the host communication, storage systems, including DDR2 SDRAM and FLASH, and provides a very powerful single slot transceiver solutions for a variety of software radio technology.
Platform: | Size: 254976 | Author: dj | Hits:

[Technology Management] 512MbDDR2

Description: micro 512Mddr2详细specification-micro ddr2 spec
Platform: | Size: 1831936 | Author: james | Hits:

[VHDL-FPGA-Verilog] ddr2_sodimm_x64_333MHz_hp2

Description: DDR2内存条（sodimm封装）的控制器设计-DDR2 controller for sodimm
Platform: | Size: 4543488 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] k4t51xx3qj_rev11

Description: 64M 三星samsung公司的ddr2芯片的数据手册，在网上难找，直接问芯片供应商要的-64M DDR2 datasheets, online hard to find, to ask directly to the chip suppliers
Platform: | Size: 693248 | Author: 陈星 | Hits:

[VHDL-FPGA-Verilog] Verilog_module

Description: micron 1G内存条verilog模型，对应具体信号为MT8HTF12864HZ-800，内存颗粒为MT47H128M8CF-25-micron 1G DDR2 SDRAM verilog module
Platform: | Size: 34816 | Author: | Hits:

[Software Engineering] MT47H128M4_MT47H64M8_MT47H32M16

Description: micron公司DDR2 SDRAM资料：MT47H128M4_MT47H64M8_MT47H32M16.pdf-micron DDR2 SDRAM：MT47H128M4_MT47H64M8_MT47H32M16.pdf
Platform: | Size: 1906688 | Author: yy | Hits:

[VHDL-FPGA-Verilog] ddr2_demo

Description: lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
Platform: | Size: 886784 | Author: 肖涛 | Hits:

[VHDL-FPGA-Verilog] 2048Mb_ddr2_verilog_model

Description: ddr2 verilog model,用于验证DDR2 Controller。-DDR2 Verilog model, and used to verify the DDR2 Controller.
Platform: | Size: 2634752 | Author: 天空 | Hits:

[VHDL-FPGA-Verilog] VmodCAM-0.0

Description: 从VMOD设想头中读入视频流数据，将其存在ddr2中，并且通过Hdmi线显示出来-Read into the video stream data from the VMOD envisaged head, exist ddr2, and the the Hdmi line displayed
Platform: | Size: 2304000 | Author: 康恺 | Hits:

[VHDL-FPGA-Verilog] FSM

Description: FPGA学习资料，新手入门资料,VERILOG- Micron SDRAM DDR2 Simulation model Verilog
Platform: | Size: 320512 | Author: liu | Hits:

[VHDL-FPGA-Verilog] ddr

Description: DDR2内存条在FPGA中的应用,包括内部结构，时序操作和注意事项。-about DDR2 APLLICATION IN FPGA，includ inner instraction timequist and attend.
Platform: | Size: 2529280 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] ddr2_sdram_latest[1].tar

Description: ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
Platform: | Size: 1779712 | Author: hxr | Hits:

[SCM] ug_ddr_sdram

Description: DDR and DDR2 SDRAM Controller Compiler 的用户向导-DDR and DDR2 SDRAM Controller Compiler User Guide
Platform: | Size: 1005568 | Author: xl | Hits:

[VHDL-FPGA-Verilog] emi(1)

Description: the external memory interface for the ddr ddr2 ddr3 sdram device
Platform: | Size: 9606144 | Author: zhenu | Hits:

[VHDL-FPGA-Verilog] xapp859_rtl

Description: xilinx PCIE IP核 包括ddr2 memory interface ML555开发板-xilinx PCIE IP cores containing ddr2 memory interface can be used on ML555 development kit
Platform: | Size: 135168 | Author: sun | Hits:

[Windows Develop] DDDRR2_sdrramD

Description: DDR2 的控制器，它是由由LATTICE的编译器生成。 -DDR2 controller, which is generated by by LATTICE the compiler.
Platform: | Size: 970752 | Author: iadmin | Hits:

[VHDL-FPGA-Verilog] test_ddr2_mem_model

Description: ddr2 test bench top for altera fpga.-ddr2 test bench top for fpga.
Platform: | Size: 4096 | Author: ShengbingChou | Hits:

[Other] npi_write

Description: 从FPGA向DDR2写入数据。采用NPI接口。单字写入。是用Verilog HDL 写的-Write data from the FPGA to DDR2. Using NPI Interface. The word is written. Is written using Verilog HDL
Platform: | Size: 320512 | Author: 许亮 | Hits:

[DSP program] ddr2

Description: dsp tmsc6455 ddr配置例程-dsp tmsc6455 ddr configuration routines
Platform: | Size: 48128 | Author: 李凤 | Hits:
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