ddr2_demo\user_logic\testbench\ddr2_demo_tb.v
.........\..........\src\ddr2_demo_top.v
.........\..........\...\ddr_ulogic.v
.........\..........\...\lfsr128.v
.........\..........\.im\modelsim\ddr2_ecp3_demo.do
.........\..........\...\........\wave.do
.........\..........\...\aldec\ddr2_ecp3_demo.do
.........\..........\...\.....\wave.do
.........\..........\par\ddr2_ecp3_spb.ldf
.........\..........\...\ddr2_ecp3_spb.lpf
.........\..........\...\ddr2_ecp3_spb.pty
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.........\..........\...\impl1\ddr2_ecp3_spb_impl1_summary.html
.........\..........\...\.....\launch_synplify.tcl
.........\..........\...\.....\stdout.log
.........\..........\...\.....\impl1_syn.prj
.........\..........\...\.....\syntmp\run_option.xml
.........\..........\...\.....\......\cmdrec_compiler.log
.........\..........\...\.....\......\impl1_flink.htm
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.........\..........\...\.....\......\impl1_toc.htm
.........\..........\...\.....\......\closed.png
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.........\..........\...\.....\......\cmdrec_premap.log
.........\..........\...\.....\......\impl1.plg
.........\..........\...\.....\......\cmdrec_fpga_mapper.log
.........\..........\...\.....\......\impl1.msg
.........\..........\...\.....\...log\report\impl1_compiler_runstatus.xml
.........\..........\...\.....\......\......\impl1_compiler_warnings.txt
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.........\..........\...\.....\......\......\impl1_premap_runstatus.xml
.........\..........\...\.....\......\......\impl1_fpga_mapper_errors.txt
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.........\..........\...\.....\......\......\impl1_fpga_mapper_runstatus.xml
.........\..........\...\.....\......\......\impl1_fpga_mapper_generated_clk.rpt
.........\..........\...\.....\......\......\impl1_fpga_mapper_timing_report.xml
.........\..........\...\.....\......\......\impl1_fpga_mapper_resourceusage.rpt
.........\..........\...\.....\......\......\impl1_fpga_mapper_area_report.xml
.........\..........\...\.....\......\......\impl1_fpga_mapper_opt_report.xml
.........\..........\...\.....\......\impl1_premap.srr
.........\..........\...\.....\......\impl1_premap.szr
.........\..........\...\.....\......\impl1_fpga_mapper.srr
.........\..........\...\.....\......\impl1_fpga_mapper.szr
.........\..........\...\.....\......\impl1_fpga_mapper.srr_Min
.........\..........\...\.....\...work\impl1_compiler.tlg
.........\..........\...\.....\.......\impl1_compiler.srs
.........\..........\...\.....\.......\impl1_premap.fse
.........\..........\...\.....\.......\impl1_premap.srd
.........\..........\...\.....\run_options.txt
.........\..........\...\.....\scratchproject.prs
.........\..........\...\.....\impl1.srr
.........\..........\...\.....\dm\impl1_compiler.xdm
.........\..........\...\.....\impl1.srl
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.........\..........\...\.....\traplog.tlg
.........\..........\...\.....\.recordref_modgen
.........\..........\...\.....\AutoConstraint_ddr2_demo_top.sdc
.........\..........\...\.....\impl1.srd
.........\..........\...\.....\impl1.srm
.........\..........\...\.....\impl1.edi
.........\..........\...\.....\impl1_synplify.lpf
.........\..........\...\.....\impl1.areasrr
.........\..........\...\.....\ddr2_ecp3_spb_impl1.edi
.........\..........\...\.....\ddr2_ecp3_spb_impl1.areasrr
.........\..........\...\.....\.build_status
.........\..........\...\reportview.xml
.........\..........\...\.spreadsheet_view.ini
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