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[VHDL-FPGA-Verilog] DDR2_Control

Description: 本源码是用FPGA控制DDR2芯片的vhdl源码，并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code
Platform: | Size: 13041664 | Author: 冯鹏飞 | Hits:

[Other] DDR2_Controller-master

Description: DDR2_Controller-master
Platform: | Size: 34816 | Author: 小黄花3333 | Hits:

[VHDL-FPGA-Verilog] vip_ex2

Description: 特权同学开发板上的例程，DDR2控制器集成与读写测试(The routines on the privileged students' development board, DDR2 controller integration and reading and writing tests)
Platform: | Size: 550912 | Author: Ienovo | Hits:

[Other] 内存pdf

Description: MT47H256M4 内存芯片手册对cpu连接内存时序要求理解 ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */ | AT91C_DDRC2_TXSNR_(27) /* 19 * 7.5 = 142.5 ns*/ | AT91C_DDRC2_TRFC_(26)); /* 18 * 7.5 = 135 ns */(ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */ ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */ | AT91C_DDRC2_TXSNR_(27) /* 19 * 7.5 = 142.5 ns*/ | AT91C_DDRC2_TRFC_(26)); /* 18 * 7.5 = 135 ns */)
Platform: | Size: 3486720 | Author: linsheng_111 | Hits:

[Other] 5692-thphn72

Description: modding ddr 2 sd ram to 800mhz
Platform: | Size: 798720 | Author: redbulx3 | Hits:

[Windows Develop] Thaiphoon_Burner_7.1.1.0

Description: Thaiphoon_Burner_7.1.1.0是一款针对内存条的SPD信息工具.thaiphoon burner可以修改或复制SPD信息，也能够完全重写SPD信息，并支持DDR2内存以及多种芯片组(Thaiphoon_Burner_7.1.1.0 is a SPD information tool for memory bars. Thaiphoon burner can modify or copy SPD information, also can completely rewrite SPD information, and support DDR2 memory and a variety of chipsets.)
Platform: | Size: 1770496 | Author: 侠侠猪 | Hits:

[Technology Management] DDR4 JEDEC standard

Description: DDR4 SDRAM Specifications from JEDEC STANDARD. ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2).
Platform: | Size: 1824071 | Author: bdebug@gmail.com | Hits:

[VHDL-FPGA-Verilog] DDR2_SDRAM操作时序

Description: DDR2_SDRAM操作时序，介绍的很详细，不错(DDR2? SDRAM operation sequence, very detailed introduction, very good)
Platform: | Size: 1936384 | Author: zou3 | Hits:

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