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[Other] cyclone3c25

Description: cyclone III系列的3c25的详细例子及其讲解 对深入学习FPGA有很大帮助-very help--cyclone 3 ep3c25
Platform: | Size: 31909888 | Author: 姜华 | Hits:

[VHDL-FPGA-Verilog] pljtest

Description: CYCLONE II　内嵌8051IP核实现等精度频率计-CYCLONE II embedded nuclear 8051IP achieve precision frequency meter, etc.
Platform: | Size: 4552704 | Author: 吴宏伟 | Hits:

[Other] TREXC1UserGuide

Description: The TREX C1 Development Kit provides everything you need to develop many digital designs using Altera Cyclone device. The Getting Started User Guide is written in a way to enable users to walk through many reference designs in 30 minutes. This chapter provides users key information about the kit.
Platform: | Size: 1845248 | Author: rfanddsp | Hits:

[VHDL-FPGA-Verilog] TrackingPresentation_jon

Description: presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s
Platform: | Size: 1514496 | Author: stjohn | Hits:

[Communication-Mobile] irig

Description: irig-b 单片机 解析 MSP430系列单片机是集成度高、超低功耗的16位单片机。Cyclone系列芯片是Altera公司推出的低价格、RAM可达288 kb的高容量的FPGA。IRIG-B码广泛应用于靶场时间信息的传递和各系统的时间同步。详细介绍了IRIG-B码解码电路和调制电路的硬件设计。MSP430的软件采用C语言编写，使程序有很强的可移植性。-irig-b microcontroller MSP430 Microcontroller analysis are highly integrated, ultra-low-power 16-bit microcontroller. Altera' s Cyclone series of chips are launched in low-cost, RAM up to 288 kb of high-capacity FPGA. IRIG-B time code range is widely used in the transmission of messages and the system time synchronization. Details of the IRIG-B decoding circuit and modulation circuit of the hardware design. MSP430 software using C language, so that programs are highly portable.
Platform: | Size: 11264 | Author: JEFF | Hits:

[VHDL-FPGA-Verilog] Cyclone_Series_Device_Thermal_Resistance

Description: cyclone系列FPGA的串行设备阻抗匹配设计指南-cyclone series FPGA Design Guide impedance matching of serial devices
Platform: | Size: 83968 | Author: xinmuwang | Hits:

[VHDL-FPGA-Verilog] sopcfpga

Description: 一个Altera Cyclone PCI开发板的配套样板源代码-Sample source code for An Altera Cyclone PCI development board
Platform: | Size: 4057088 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] cyclone_handbook

Description: Altera 公司生产的FPGA系列中的低端高性能产品cyclone一代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone generation, user manuals, this is also downloaded from the Altera website.
Platform: | Size: 3013632 | Author: carris | Hits:

[VHDL-FPGA-Verilog] cyclone2_handbook

Description: Altera 公司生产的FPGA系列中的低端高性能产品cyclone二代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone II user' s manual, this is also downloaded from the Altera website.
Platform: | Size: 3330048 | Author: carris | Hits:

[SCM] protel_altera_pcb_sch_lib

Description: altera cyclone 系列的protel封装图，layout的哥们有用的~-altera cyclone series of protel package diagram, layout useful ~
Platform: | Size: 661504 | Author: cream | Hits:

[Other] EP3C120

Description: EP3C120的官方开发板原理图，cyclone iii 系列最大的FPGA.-EP3C120s official development board schematics, cyclone iii series of the largest FPGA.
Platform: | Size: 1176576 | Author: shuirenmu | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

[VHDL-FPGA-Verilog] FPGA_AD

Description: 基于 Cyclone EP1C6240C8 FPGA的ADS2807接口程序，主要用来使用FPGA控制ADS2807的采集。 采用FPGA来模拟ADS2807的时序来实现控制功能。 提供采样频率控制、AD通道转换、采样数据缓存等功能。-Cyclone EP1C6240C8 FPGA-based interface program of the ADS2807, ADS2807 is mainly used to control the use of FPGA collection. ADS2807 with FPGA to simulate the timing to achieve control functions. To provide sampling frequency control, AD-channel conversion, sampled-data caching and other functions.
Platform: | Size: 246784 | Author: icemoon1987 | Hits:

[VHDL-FPGA-Verilog] FPGA_ADDA

Description: 基于 Cyclone EP1C6240C8的ADS2807，DAC2902 测试程序。主要用来使用FPGA控制ADC采集和DAC的输出，从而达到高频率信号处理的功能。首先从ADC2807采集数据，然后送给DAC2902输出。 采用FPGA口线模拟ADC2807和DAC2902的时序来实现。 提供ADC采样频率控制、DAC输出频率控制、输出波形控制、ADC通道转换、DAC通道转换等功能。-Based on Cyclone EP1C6240C8 of the ADS2807, DAC2902 testing procedures. ADC is mainly used to control the use of FPGA acquisition and DAC output, so as to achieve high-frequency signal processing functions. First, from ADC2807 data acquisition, and then sent to DAC2902 output. FPGA I lines using analog timing ADC2807 and DAC2902 to achieve. ADC sampling frequency control to provide, DAC output frequency control, output waveform control, ADC channel conversion, DAC channel conversion functions.
Platform: | Size: 2019328 | Author: icemoon1987 | Hits:

[Embeded-SCM Develop] nios_lcd_3c120

Description: Cyclone III FPGA Nios II LCD开发程序，包括QuartusII工程及Verilog源码。-Cyclone III FPGA Nios II LCD development process, including the QuartusII engineering and source code.
Platform: | Size: 3079168 | Author: wei | Hits:

[Other] cycloneIII_useful_SCH

Description: cyclone III 原理图，很实用的原理图，找了很长时间才找到-cyclone III schematic, it is useful schematic, looking for a very long time to find
Platform: | Size: 64512 | Author: liqiang | Hits:

[VHDL-FPGA-Verilog] CyclonePLL

Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。 -Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
Platform: | Size: 553984 | Author: 裴雷 | Hits:

[VHDL-FPGA-Verilog] VGA_v

Description: 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input CLK_50 input RST_N //////////////////////// VGA //////////////////////////// output VGA_CLK // VGA Clock output VGA_HS // VGA H_SYNC output VGA_VS1 // VGA V_SYNC output VGA_BLANK // VGA BLANK output VGA_SYNC // VGA SYNC output [9:0] VGA_R // VGA Red[9:0] output [9:0] VGA_G // VGA Green[9:0] output [9:0] VGA_B // VGA Blue[9:0]
Platform: | Size: 520192 | Author: 林锦鸿 | Hits:

[Other] AlteraCycloneIIFPGAStarterBoard

Description: Altera Cyclone II FPGA Starter Board
Platform: | Size: 236544 | Author: | Hits:

[Other] Bufor

Description: Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
Platform: | Size: 515072 | Author: Kozinio | Hits:
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