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Description: 本文介绍了一种全新的LED显示屏控制解决方案，主要使用Altera cyclone飓风FPGA和16位凌阳单片机SPCE061A作为主控器件，采用较普遍的74LS595作为LED 显示屏显示驱动芯片。-In this paper, a new LED display control solution, the main use of Altera cyclone hurricane FPGA and 16-bit single-chip Sunplus SPCE061A as a master device, using the more common 74LS595 as an LED screen display driver chip.
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Size: 370688 |
Author: 上官婉儿 |
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Description: Altra的Cyclone系列的PCB封装-Altra
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Size: 41984 |
Author: 王者 |
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Description: 以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等-Cyclone in series as the core EP2C5Q208 experimental procedure. Including water lights, I2C memory. SPI memory, digital control, serial port, LCD, etc.
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Size: 2980864 |
Author: sarah |
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Description: cyclone II 208c8编写的 图像采集 显示程序。-cyclone II 208c8 prepared display image acquisition procedures.
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Size: 1799168 |
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Description: 基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信
所用语言位verilog HDL-QUARTUSII software implementation based on FPGA (ATERA CYCLONE II series) with SD Card SD mode digital communication language verilog HDL
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Size: 5064704 |
Author: chenbinjie |
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Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
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Size: 10240 |
Author: David.Mr.Liu |
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Description: 基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.-CYCLONE II based on the procedure, DDS Function Generator principle. Realize the use of look-up table method. Members may refer to.
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Size: 231424 |
Author: Yin |
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Description: SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck-SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
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Size: 8192 |
Author: tuya |
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Description: 1，原创 cyclone 2开发板，希望能对FPGA电子爱好者有一点设计帮助。
2，本PCB可以与开发者自己的PCB实现扩展。
3，注意接口已经提供5v,-5v，+3.3v,+1.2v输出。
4，带一个LED显示器，多路拨动开关，一个复位健。
5，晶振源兼容5种封装，其中一种是支持9v、5W高精度恒温晶振。
6，fpga内部2个PLL相互连接可以实现0－200MHz内任意频率输出。
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Size: 529408 |
Author: M |
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Description: 这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过-This is a VHDL language used to describe auto-configuration of the I2C module, the use of the I2C from opencores.org nucleus, the cyclone in the altera-chip debugging through
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Size: 7168 |
Author: wgy |
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Description: 利用ALTERA公司Cyclone II 2C35 fpga芯片，实现以太网通信。以太网芯片为DM9000A-ALTERA companies use Cyclone II 2C35 fpga chips, Ethernet communications. Ethernet chips DM9000A
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Size: 550912 |
Author: 叶志全 |
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Description: FPGA开发板的原理图很详细的，主要是ALTERA公司的CYCLONE，用protel画的，-FPGA development board schematic diagram of a very detailed, mainly ALTERA company CYCLONE, using Protel painting,
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Size: 6728704 |
Author: wangbo |
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Description: nios 中读写sdram的程序，适用于epc2 cyclone二代FPGA板子-Nios SDRAM read and write the procedures applicable to epc2 cyclone II FPGA board
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Size: 481280 |
Author: 肖文 |
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Description: cyclone III EP3C25 开发板原理图,包括flash, sdram, usb, ethernet 等接口电路，可作设计参考。-cyclone III EP3C25 development board schematic diagram, including flash, sdram, usb, ethernet interface circuit, etc., can be used for design.
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Size: 264192 |
Author: txs |
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Description: Cyclone® III EP3C25的资料-Cyclone 庐 III EP3C25 information
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Size: 527360 |
Author: 杨洋 |
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Description: 5款ALTERA FPGA开发板原理图合集。包括EP1C6Q240C6开发板原理图、Cyclone II EP2C20 原理图。希望对大家有用-5 ALTERA FPGA development board schematic diagram collection. Including EP1C6Q240C6 development board schematics, Cyclone II EP2C20 Schematic. I hope all of you a useful
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Size: 666624 |
Author: 傅佩龙 |
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Description: Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
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Size: 389120 |
Author: wmy |
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Description: 超强国际象棋引擎，编码非常规范。便于分析和使用-Super chess engine, very norms coding. Facilitate the analysis and use of
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Size: 80896 |
Author: |
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Description: The Cyclone® III PCI development board provides a hardware platform for developing and
prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a
high-density of the memory to facilitate the design and development of FPGA designs which need
huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of
the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.-The Cyclone ? III PCI development board provides a hardware platform for developing andprototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides ahigh-density of the memory to facilitate the design and development of FPGA designs which needhuge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface ofthe High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
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Size: 2132992 |
Author: 张治国 |
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Description: 一个cyclone板的原理图，cyclone型号是：ep1c20f400c8-A cyclone board schematics, cyclone model is: ep1c20f400c8
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Size: 228352 |
Author: 林熙鹏 |
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