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Description:
Platform: |
Size: 503808 |
Author: helei_zju |
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Description: altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。-altera
Platform: |
Size: 15360 |
Author: 朱峰 |
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Description: 这是一个fft的IP核,安装要求为quartus6.0以上。解压安装后可在quartus里例化使用,元件主要为cyclone和stratix,最大支持1024点的转换。
Platform: |
Size: 8719360 |
Author: 李杰 |
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Description: sopc开发板标准NIOSII模块,用于EP1C6Q240C8芯片(FPGA)-SOPC development board NIOSII standard module for EP1C6Q240C8 chip (FPGA)
Platform: |
Size: 645120 |
Author: 石林 |
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Description: this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: |
Size: 43008 |
Author: ngzhongsyen |
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Description: FPGA flash 编程序,使用CYCLONE和FLASH-FPGA flash-programmed, the use of CYCLONE and FLASH
Platform: |
Size: 318464 |
Author: chunlin_lai |
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Description: 重要代码,FPGA CYCLONE FLASH DRIVER
Platform: |
Size: 21504 |
Author: CHUNLIN_LAI |
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Description: 基于ALTERA 公司cyclone系列FPGA的程序,verilog 实现加法器-ALTERA company based FPGA family of cyclone procedures, verilog adder realize
Platform: |
Size: 209920 |
Author: 陶德杰 |
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Description: 在cycloneII里实现对FFT的硬件加速,包括所有的说明和源码-In cycloneII achieve hardware acceleration for FFT, including all instructions and source code
Platform: |
Size: 37888 |
Author: 韩启祥 |
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Description: CycloneII_NiosII的实验板资料,正在学习FPGA的可以参考一下-Experimental CycloneII_NiosII plate information, are learning FPGA
Platform: |
Size: 36268032 |
Author: shang |
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Description: Altera CycloneIII_Starter_Kit 开发板原理图-Altera CycloneIII_Starter_Kit development board schematics
Platform: |
Size: 264192 |
Author: |
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Description: 采用CPLD来培植ALTERA公司的CYCLONE系列FPGA,(AS,PS,FAS)可选-CPLD used to cultivate ALTERA company CYCLONE series FPGA, (AS, PS, FAS) optional
Platform: |
Size: 13312 |
Author: 梁光辉 |
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Description: DVB系统的SDI数据数据传输接口,FPGA设计实现-DVB system SDI data transmission interface, FPGA Design and Implementation
Platform: |
Size: 229376 |
Author: 梁光辉 |
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Description: 一个实现简单的数字锁相环Verilog代码,本人借鉴网上现有的代码后经修改在Cyclone II上调通实现,里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: |
Size: 67584 |
Author: |
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Description:
Platform: |
Size: 2251776 |
Author: 火冰 |
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Description: 用verilog写的HC164的驱动程序,参考了Xilinx的经典算法,做了一点改进~~~很通用,是初学verilog以及FPGA开发很有用的一个程序!
Platform: |
Size: 3072 |
Author: 屠宁杰 |
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Description: 在SOPC平台上,开发得MP3源代码,包括mp3软解码,图形界面!还包括了TFT,PWM的IP!-In SOPC platform, the development of a MP3 source code, including mp3 soft decoding, graphical interface! Also includes a TFT, PWM s IP!
Platform: |
Size: 1692672 |
Author: lrt |
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Description: Cyclone1C20的Nios开发板完整原理图Protel格式-Cyclone1C20 integrity of the Nios development board schematics Protel format
Platform: |
Size: 157696 |
Author: 李文俊 |
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Description: 利用VHDL语言实现在,altera 公司的cyclone芯片上实现数字信号的2psk调制解调功能-The use of VHDL language to achieve, altera s cyclone chip digital signal modulation and demodulation functions 2psk
Platform: |
Size: 293888 |
Author: 叶峰 |
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Description: 这个是地理教案制作中的气旋与反气旋的flash源码-This is a geography lesson plans produced in the cyclone and the anticyclone over the flash source
Platform: |
Size: 281600 |
Author: wangping |
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