Location:
Search - cpld
Search list
Description: CPLD对DUSH的读写控制,LINUX下运行.解压即可.-CPLD controls R/W of DUSH. Run in LINUX. Ready to use after unzipped.
Platform: |
Size: 3072 |
Author: 看 |
Hits:
Description: 这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
Platform: |
Size: 1689600 |
Author: 开心火 |
Hits:
Description: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Platform: |
Size: 120832 |
Author: |
Hits:
Description: 8051的IP软核，使用硬件描述语言编写，可以下载到FPGA/CPLD中作为片上系统的处理器-8051 IP soft-core, the use of hardware description language can be downloaded to the FPGA/CPLD as a system-on-chip processor
Platform: |
Size: 532480 |
Author: zy |
Hits:
Description: 服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).-server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
Platform: |
Size: 526336 |
Author: 老罗 |
Hits:
Description: DSP2407上实现数控IO功能的C语言源程序，此程序与硬件有关（使用了CPLD），但测试部分有一定参考价值。
-DSP2407 NC IO on the C language function source, this procedure with the hardware (using the CPLD), but there are certain tests of some reference value.
Platform: |
Size: 14336 |
Author: |
Hits:
Description: 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD/FPGA achieve floating-point computation methods
Platform: |
Size: 82944 |
Author: wei |
Hits:
Description: 51单片机系统扩展超大容量存储器接口设计的cpld源码。-51 MCU expansion of super-capacity memory interface design cpld source.
Platform: |
Size: 56320 |
Author: 曾卫华 |
Hits:
Description: 广州致远电子的LA系列逻辑分析仪的详细使用指南。详细介绍了如何在CPLD/FPGA/单片机开发，嵌入式开发，数字电路开发等方面使用逻辑分析仪。是上述开发中一个非常有用的工具！
逻辑分析仪——纵观全局、掌控细节——细节决定成败！-Guangzhou, Zhi Yuan Electronics LA Series logic analyzer detailed guidelines for their use. Details of how the CPLD/FPGA/microcontroller development, embedded development, the development of digital circuits use a logic analyzer. This development is a very useful tool! Logic analyzer-- Overall, control of the details-- details determine the success or failure!
Platform: |
Size: 3083264 |
Author: 徐勇 |
Hits:
Description: 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
Platform: |
Size: 205824 |
Author: 冰激凌 |
Hits:
Description: CPLD的程序，用住于虚心的学习神经网络模式识别及其实现-CPLD procedures used to live modestly in the learning neural network and pattern recognition to achieve
Platform: |
Size: 1074176 |
Author: 李翔 |
Hits:
Description: 单片机和cpld综合应用的示例，可以通过本程序学习如何利用单片机和cpld的综合应用，其中单片机的程学编写随后就会上传上来-SCM and cpld comprehensive application example, through this program to learn how to use SCM and cpld integrated applications, MCU-school preparation will be uploaded onto the subsequent
Platform: |
Size: 19456 |
Author: 李恒 |
Hits:
Description: 条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能-screen controller CPLD programming, the major shift register, the encoder and decoder functions
Platform: |
Size: 410624 |
Author: 阿九 |
Hits:
Description: cpld,非常好用的源码.可以为你带来方便.-cpld, very user-friendly source. You can bring convenience.
Platform: |
Size: 414720 |
Author: |
Hits:
Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。
以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。
-JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: |
Size: 2048 |
Author: 李伟 |
Hits:
Description: 有关于VHDL举例,FPGA/CPLD的运用方面的例子-for example VHDL, FPGA/CPLD to the use of the example
Platform: |
Size: 198656 |
Author: 许宏亮 |
Hits:
Description: VHDL的基础知识,一切从基础开始!希望这个对大家有所帮助!-VHDL basic knowledge, everything from the foundation started! We hope that the right help!
Platform: |
Size: 30720 |
Author: 老纪 |
Hits:
Description: XilinxJTAG.rar
xilinx CPLD,FPGA的JTAG口使用说明.-XilinxJTAG.rar Xilinx CPLD, FPGA JTAG I use.
Platform: |
Size: 431104 |
Author: |
Hits:
Description: 关于CPLD的文章 不错的! 可以给菜菜参考下-article on the CPLD good! Can either under reference
Platform: |
Size: 17325056 |
Author: 许辉 |
Hits:
Description: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，通过编译、仿真，并下载到CPLD器件上进行编程制作，实现交通灯系统的控制过程。EDA技术是用于电子产品设计中比较先进的技术，可以代替设计者完成电子系统设计中的大部分工作，而且可以直接从程序中修改错误及系统功能而不需要硬件电路的支持，既缩短了研发周期，又大大节约了成本，受到了电子工程师的青睐。实现路口交通灯系统的控制方法很多，可以用标准逻辑器件、可编程序控制器PLC、单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持，在一定程度上增加了功能修改及系统调试的困难。因此，在设计中采用EDA技术，应用目前广泛应用的VHDL硬件电路描述语言，实现交通灯系统控制器的设计，利用MAXPLUSⅡ集成开发环境进行综合、仿真，并下载到CPLD可编程逻辑器件中，完成系统的控制作用。-the current design was chosen over a wide range of VHDL hardware description language circuit. Implementation of traffic lights at the junction of the controller hardware circuit description, compiler, simulation, to download and CPLD programming on production, traffic signal system to achieve the control process. EDA technology is used to design electronic products more advanced technology, designers can replace the complete electronic system design most of the work, but can directly from the process to amend the mistakes and system functions without the need for hardware circuits of support, both to shorten the development cycle, another significant cost savings by the electronic engineers of all ages. Achieving junction traffic signal system control many ways, using standard logic devic
Platform: |
Size: 4096 |
Author: jazvy |
Hits: