VHDL-FPGA-Verilog List Page 971

VHDL-FPGA-Verilog list

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VGA800 Downloaded：0: The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be tested for color stripe.
Date : 2025-08-06 Size : 7.54mb User : 普尔
UART Downloaded：0: The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personall
Date : 2025-08-06 Size : 17.04mb User : 普尔
timer Downloaded：0: The code to use verilog language to describe, in nios on operation, to achieve the timer settings and interrupt operation, combined with the timestamp reads the program run.
Date : 2025-08-06 Size : 18.38mb User : 普尔
Huffman-Encoder Downloaded：0: The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.
Date : 2025-08-06 Size : 11.3mb User : 普尔
ps2_FSM Downloaded：0: This program is used to describe the mouse function on the FPGA board and it is very useful for the beginner on the FPGA board.
Date : 2025-08-06 Size : 1kb User : jiangtao
VHDL-based-music-player-design Downloaded：0: For the I semester of 2012 EDA large operations, including design documentation and source code. The designed system is difficult to find online (at that time I did not find, in particular, is the source), two systems bu
Date : 2025-08-06 Size : 4.7mb User : 刘志
sdram Downloaded：0: This procedure in Quartus ii environment development and design of SDRAM control module, complete functions correctly, the SDRAM read and write correctly
Date : 2025-08-06 Size : 4.53mb User : zhu
verilog_lcd Downloaded：0: In Quartus ii environment to achieve the control functions of the LCD module, the program described by the verilog hdl language, tested, this module functions in line with expectations.
Date : 2025-08-06 Size : 4.11mb User : zhu
verilog_ps2 Downloaded：0: In Quartus ii environment to achieve the PS2 module control functions, procedures described by the verilog hdl language, tested, this module functions in line with expectations.
Date : 2025-08-06 Size : 3.18mb User : zhu
verilog_vga Downloaded：0: In quartus ii development environment to achieve the vga module control functions have been tested, the module can generate correct timing, functionality consistent with the intended function.
Date : 2025-08-06 Size : 3.7mb User : zhu
10_uart Downloaded：0: In quartus ii development environment to achieve the uart serial communication module control functions have been tested, the module can generate correct timing, functionality consistent with the intended function.
Date : 2025-08-06 Size : 6.27mb User : zhu
jtag Downloaded：1: verilog language jtag (boundary scan module), a novice when you can look
Date : 2025-08-06 Size : 425kb User : 张一凡

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