VHDL-FPGA-Verilog List Page 970

VHDL-FPGA-Verilog list

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fifo Downloaded：0: Synchronous fifo, use ISE13.4 V5 device speed 550MHz
Date : 2025-08-06 Size : 1kb User : jj
usbfifo Downloaded：0: A transfor way for USB，control the data to endpoint.
Date : 2025-08-06 Size : 1kb User : Tom
DoubleRoad Downloaded：0: The FPGA program written in VHDL, run in the ISE, simulation, design a kind of CCD acquisition scheme
Date : 2025-08-06 Size : 2kb User : Tom
ADC Downloaded：0: VHDL编写的同步时序逻辑程序，实现AD的数据采集，已经通过仿真。
Date : 2025-08-06 Size : 2kb User : Tom
vhdldelay Downloaded：0: Use VHDL to write a software delay, use, can set the delay time.
Date : 2025-08-06 Size : 1kb User : Tom
fourroadccd Downloaded：0: A CCD acquisition mode, collection, each road 12, thinking the 48 high-speed transmission at the same time.
Date : 2025-08-06 Size : 2kb User : Tom
ram_data Downloaded：0: A RAM are connected to the USB, the test data transmission, use the start development board has been tested successfully.
Date : 2025-08-06 Size : 1kb User : Tom
sddrive Downloaded：0: sd card driver
Date : 2025-08-06 Size : 64kb User : 何其
AD-TLC2543 Downloaded：0: AD TLC2543
Date : 2025-08-06 Size : 5.59mb User : sulianghe
VGAcolor Downloaded：0: VGA display Verilog procedures, ideal for beginners, this program uses Kang core chamber, you can change the lock pin.
Date : 2025-08-06 Size : 1.48mb User : 林月
cordic6 Downloaded：0: digital lock
Date : 2025-08-06 Size : 2.39mb User : 王旭
DEADTIME510 Downloaded：0: Produces full-bridge inverter circuit driving pulse signal, to ensure that the dead time, and with the input signal frequency changes.
Date : 2025-08-06 Size : 1.99mb User : clm

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