VHDL-FPGA-Verilog List Page 975

VHDL-FPGA-Verilog list

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multi_cpu Downloaded：0: Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
Date : 2025-08-06 Size : 2.13mb User : 张宇轩
lab5 Downloaded：0: Developed by xilinx ISE14.3 single-cycle CPU system, facing the spartan Ⅲ board simulation debugging and practical tests have passed.
Date : 2025-08-06 Size : 2.92mb User : 张宇轩
KEY4X4_1 Downloaded：0: CPLD/FPGA, VHDL language keyboard button scanning, keyboard scanning procedures
Date : 2025-08-06 Size : 256kb User : 孙祥
lab2parte1 Downloaded：0: We want to show the values set through the switches SW8-1 on the 7-segment display and HEX0 Hex1. Values are denoted SW4 and SW8-5-one, shown in Hex1 and diplays HEX0, respectively. Your circuit must
Date : 2025-08-06 Size : 1kb User : Lais
AD9226 Downloaded：0: An AD9226 chip driver, FPGA written. Though simple, but I hope you will help
Date : 2025-08-06 Size : 1.33mb User : 王凌
AD9764 Downloaded：0: An AD9764 FPGA-based drive, we want to help a friend in need
Date : 2025-08-06 Size : 1.36mb User : 王凌
cc Downloaded：0: To write a simple function analog telephone billing code, Verilog, using the Xilinx Spartan 3E
Date : 2025-08-06 Size : 1.62mb User : 蔡青青
LCD12864 Downloaded：0: The use of language LCD1602 display
Date : 2025-08-06 Size : 413kb User : 王明
cpu Downloaded：0: Eight experiments designed CPU design using the instruction set, write assembly code in order to test all commands and instructions that involve the design of related functions. Design a good test of the assembly code, a
Date : 2025-08-06 Size : 3.22mb User : Bingo
rom_mem Downloaded：0: Design 146 of the ROM, the structure shown in Figure 1. Which, reset the reset button, you can use TEC-CA platform reset pulse, corresponding ACEX1K100 model chip pin ID is 83, Cyclone compared to 240 clock as clock sour
Date : 2025-08-06 Size : 107kb User : Bingo
asynram Downloaded：0: Design 326 of RAM, the structure shown in Figure 2. Which, adr as address pins, cs, wr, rd, respectively, for the chip select, write and read the pin, din_out to input or output pin. When cs = 0 and wr from low to high (
Date : 2025-08-06 Size : 331kb User : Bingo
zsjk Downloaded：0: According to different water requirements, flexibility preset different injection time, real-time monitoring and dynamic visual display of the current injection time information, when the injection is complete, provide r
Date : 2025-08-06 Size : 1kb User : reder

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