VHDL-FPGA-Verilog List Page 977

VHDL-FPGA-Verilog list

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freq_4 Downloaded：0: 4 divided clock, synchronization, with clear function. Can be used for clock divider design
Date : 2025-08-07 Size : 22kb User : 梅梅
multt Downloaded：0: The program implements a 16* 16 multiplier, multiplier design can be used as reference
Date : 2025-08-07 Size : 23kb User : 梅梅
16_QAM Downloaded：0: a great complied code of 16QAM modulation for OFDM
Date : 2025-08-07 Size : 1kb User : 罗月
data_scramble Downloaded：0: a great complied code of data sramble for OFDM
Date : 2025-08-07 Size : 1kb User : 罗月
CP_adder Downloaded：0: a great complied code of cyclic prefix for OFDM which is good for intersymbol interference and inter channel interference
Date : 2025-08-07 Size : 1kb User : 罗月
FPGA--AD9854 Downloaded：1: Using FPGA technology to achieve control AD9854 generate various waveforms.
Date : 2025-08-07 Size : 4.1mb User : 郭
Freq_Count_Test-8.15 Downloaded：0: Verlag code, frequency meter, calculate the input trigger signal frequency, frequency = operating clock/count the results.
Date : 2025-08-07 Size : 4.38mb User : Kg5
LAB2 Downloaded：0: STEP BY STEP STUDY ZedBoard & Zynq
Date : 2025-08-07 Size : 194kb User : 刘玉顺
Lab3 Downloaded：0: STEP BY STEP STUDY ZedBoard & Zynq
Date : 2025-08-07 Size : 4.18mb User : 刘玉顺
moshuzhuanhuan1111 Downloaded：0: Analog-to-digital conversion, eight road parallel data cached in FIFO, and output. By sequential control of A/D chip acquisition speed, and ARM board receives the speed.
Date : 2025-08-07 Size : 851kb User : 夏天翔
WISHBONE_conmax Downloaded：0: Very detailed wishbone bus to learn from the code and documentation
Date : 2025-08-07 Size : 651kb User : haizi
counter_99 Downloaded：0: XINLIX soprtan3 source code to achieve the counter function, counting and addition and subtraction on the digital display, adjustable counting interval.
Date : 2025-08-07 Size : 861kb User : TSWC

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