VHDL-FPGA-Verilog List Page 976

VHDL-FPGA-Verilog list

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output_10014537 Downloaded：0: XINLIX SPORTAN3 FPGA in the digital tube display scroll figures can be set free, program design clock divider, etc.
Date : 2025-08-07 Size : 1.25mb User : TSWC
tswc_state Downloaded：0: XILINX SPORTAN3 implement state machine function, state switch, the switching time may be changed.
Date : 2025-08-07 Size : 1.23mb User : TSWC
weiji Downloaded：0: FPGA-based UART design, fpga design simple baud rate generator
Date : 2025-08-07 Size : 1kb User : 孟一
FPGA6_LCDaUART Downloaded：0: Based on the FPGA Verilog LCD display serial data
Date : 2025-08-07 Size : 1.35mb User : 宋贵来
FPGA7_UART Downloaded：0: Based on the FPGA Verilog UART interface data transfer
Date : 2025-08-07 Size : 842kb User : 宋贵来
FPGA9_VGAaUART Downloaded：0: Based on the FPGA Verilog VGA display UART data
Date : 2025-08-07 Size : 914kb User : 宋贵来
FPGA11_DAC Downloaded：0: Based on the FPGA Verilog buttons adjust the DAC
Date : 2025-08-07 Size : 4.54mb User : 宋贵来
FPGA12_I2C Downloaded：0: Based on the FPGA Verilog I2C interface communication
Date : 2025-08-07 Size : 3.04mb User : 宋贵来
FPGA13_SDRAM Downloaded：0: Based on the FPGA Verilog SDRAM words communication
Date : 2025-08-07 Size : 2.46mb User : 宋贵来
edge_catch Downloaded：0: signal process jitter
Date : 2025-08-07 Size : 1kb User : ouyangxishu
FPGA Downloaded：0: FPGA development technology-related information can be provided to the novice, the hand used to deepen the study of relevant content.
Date : 2025-08-07 Size : 2mb User : Dongbing
Regfile Downloaded：0: Use Xilinx ISE14.3, using Verilog HDL language of computers and register file program, Spartan Ⅲ board through debugging.
Date : 2025-08-07 Size : 1.1mb User : 张宇轩

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