VHDL-FPGA-Verilog List Page 966

VHDL-FPGA-Verilog list

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cordic Downloaded：0: Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available
Date : 2025-08-06 Size : 3.58mb User : 刘淇
CORDIC_vhdl Downloaded：0: Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available
Date : 2025-08-06 Size : 3.58mb User : 刘淇
LCD1602 Downloaded：0: LCD1602 of the FPGA verilog code, quartus compiled by
Date : 2025-08-06 Size : 5.45mb User : 王强
DDS Downloaded：0: Based on FPGA and stm32 arbitrary waveform generator, full touch implementation. Useful information ah, 2001 electric race title
Date : 2025-08-06 Size : 8.36mb User : 刘华
FSK Downloaded：0: This procedure using VHDL language is based on the principle of DDS achieve FSK modulation
Date : 2025-08-06 Size : 287kb User : 张志强
EZ_USB_LOOPBACK Downloaded：0: This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write
Date : 2025-08-06 Size : 2kb User : 陈培哲
LCD Downloaded：0: Lit spartan-3e success on the LCD module display OK!
Date : 2025-08-06 Size : 2kb User :
Verilog_seg7 Downloaded：0: The mixed input method of schematic File and Verilog HDL File for Quartus
Date : 2025-08-06 Size : 2.89mb User : 杨勇
temp Downloaded：0: With fpga/cpld drive temperature sensor lm75, with digital display temperature
Date : 2025-08-06 Size : 234kb User : 刘慧忠
CRC Downloaded：0: CRC 8bit for bus monitor
Date : 2025-08-06 Size : 1kb User : 郭涛
CRC.vhd Downloaded：0: CRC 8bit for bus monitor
Date : 2025-08-06 Size : 1kb User : 郭涛
zuoye2 Downloaded：0: Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.
Date : 2025-08-06 Size : 3.56mb User : 林源

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