VHDL-FPGA-Verilog List Page 967

VHDL-FPGA-Verilog list

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decode38 Downloaded：0: Encoder 38 code, FPGA implementation, language Verilog prepared
Date : 2025-08-06 Size : 214kb User : 谢凯聪
latch Downloaded：0: FPGA latches code, EPM240 has been verified, you can learn to use, with the Verilog language
Date : 2025-08-06 Size : 114kb User : 谢凯聪
ad_dosth Downloaded：0: Achieve a Xilinx FPGA reads AD then DA output, AD, DA are parallel
Date : 2025-08-06 Size : 19.08mb User : 张兴
rom_fft Downloaded：0: Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt
Date : 2025-08-06 Size : 19.86mb User : 张兴
edc_spi Downloaded：0: Electronic Design Contest, the microcontroller and FPGA serial communication program, more stable performance tested
Date : 2025-08-06 Size : 1.75mb User : 张兴
fir_test Downloaded：0: Conducted using xilinx FPGA FIR filter design
Date : 2025-08-06 Size : 1009kb User : 张兴
edc_spi_command Downloaded：0: MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pa
Date : 2025-08-06 Size : 832kb User : 张兴
dac904_lock Downloaded：0: Using the xilinx FPGA-DCM IP core for the development of DA procedures.
Date : 2025-08-06 Size : 707kb User : 张兴
edc01_1 Downloaded：0: Produced using the xilinx FPGA frequency measurement module, microcontroller via the parallel port pa
Date : 2025-08-06 Size : 7.92mb User : 张兴
programable_fir Downloaded：0: Variable parameters using xilinx FIR filter
Date : 2025-08-06 Size : 4.78mb User : 张兴
edc_stm32_dds Downloaded：0: stm32 write DDS AD9854 ca
Date : 2025-08-06 Size : 22.06mb User : 张兴
clock Downloaded：0: Based vhdl digital clock, timer alarm, you can tune in minutes, hours
Date : 2025-08-06 Size : 1.1mb User : songlinzhan

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