Achieve a Xilinx FPGA reads AD then DA output, AD, DA are parallel

ad_dosth
........\0810.cpj
........\AD_control.vhd
........\DA_control.vhd
........\_ngo
........\....\cs_icon_pro
........\....\...........\_xmsgs
........\....\...........\......\xst.xmsgs
........\....\...........\coregen.cgc
........\....\...........\coregen.cgp
........\....\...........\coregen.log
........\....\...........\generate_icon_pro.xco
........\....\...........\icon_pro.gise
........\....\...........\icon_pro.ucf
........\....\...........\icon_pro.vhd
........\....\...........\icon_pro.vho
........\....\...........\icon_pro.xco
........\....\...........\icon_pro.xise
........\....\...........\icon_pro_flist.txt
........\....\...........\icon_pro_readme.txt
........\....\...........\icon_pro_xmdf.tcl
........\....\...........\tmp
........\....\...........\...\_cg
........\....\...........\...\_xmsgs
........\....\...........\...\......\pn_parser.xmsgs
........\....\cs_ila_pro_0
........\....\............\_xmsgs
........\....\............\......\xst.xmsgs
........\....\............\coregen.cgc
........\....\............\coregen.cgp
........\....\............\coregen.log
........\....\............\generate_ila_pro_0.xco
........\....\............\ila_pro_0.cdc
........\....\............\ila_pro_0.gise
........\....\............\ila_pro_0.ucf
........\....\............\ila_pro_0.vhd
........\....\............\ila_pro_0.vho
........\....\............\ila_pro_0.xco
........\....\............\ila_pro_0.xise
........\....\............\ila_pro_0_flist.txt
........\....\............\ila_pro_0_readme.txt
........\....\............\ila_pro_0_xmdf.tcl
........\....\............\tmp
........\....\............\...\_cg
........\....\............\...\_xmsgs
........\....\............\...\......\pn_parser.xmsgs
........\....\icon_pro.ngc
........\....\ila_pro_0.ngc
........\....\netlist.lst
........\....\spi_slave_cs_signalbrowser.ngo
........\....\spi_slave_cs_signalbrowser.ver
........\_xmsgs
........\......\bitgen.xmsgs
........\......\cg.xmsgs
........\......\map.xmsgs
........\......\ngcbuild.xmsgs
........\......\ngdbuild.xmsgs
........\......\par.xmsgs
........\......\pn_parser.xmsgs
........\......\trce.xmsgs
........\......\xst.xmsgs
........\ad_dosth.gise
........\ad_dosth.xise
........\clk_wiz_v3_6_readme.txt
........\clk_wiz_v3_6_vinfo.html
........\clock_wizard
........\............\clk_wiz_v3_6_readme.txt
........\............\doc
........\............\...\clk_wiz_v3_6_readme.txt
........\............\...\clk_wiz_v3_6_vinfo.html
........\............\...\pg065_clk_wiz.pdf
........\............\example_design
........\............\..............\clock_wizard_exdes.ucf
........\............\..............\clock_wizard_exdes.vhd
........\............\..............\clock_wizard_exdes.xdc
........\............\implement
........\............\.........\implement.bat
........\............\.........\implement.sh
........\............\.........\planAhead_ise.bat
........\............\.........\planAhead_ise.sh
........\............\.........\planAhead_ise.tcl
........\............\.........\planAhead_rdn.bat
........\............\.........\planAhead_rdn.sh
........\............\.........\planAhead_rdn.tcl
........\............\.........\xst.prj
........\............\.........\xst.scr
........\............\simulation
........\............\..........\clock_wizard_tb.vhd
........\............\..........\functional
........\............\..........\..........\simcmds.tcl
........\............\..........\..........\simulate_isim.bat
........\............\..........\..........\simulate_isim.sh
........\............\..........\..........\simulate_mti.bat
........\............\..........\..........\simulate_mti.do
........\............\..........\..........\simulate_mti.sh
........\............\..........\..........\simulate_ncsim.sh
........\............\..........\..........\simulate_vcs.sh
........\............\..........\..........\wave.do
........\............\..........\..........\wave.sv
........\............\..........\timing

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