VHDL-FPGA-Verilog List Page 826

VHDL-FPGA-Verilog list

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2FSK_tiaozhi Downloaded：0: To write a team 2FSK analog modulation procedures (a sinusoidal carrier in the form of output, sampling quantified), definitely run out
Date : 2025-07-23 Size : 491kb User : 张健
8-bit-RISC_CPU Downloaded：0: 8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
Date : 2025-07-23 Size : 186kb User :
ov7670 Downloaded：0: OV7670 driver code (source) only for the driver code, the output pixel signal, there must be a corresponding lower module to fully complete camera control
Date : 2025-07-23 Size : 8kb User : 张安
I2C Downloaded：0: I2C control source signal transmission and control for the camera. When using the pull-up resistor connected FPGA requires otherwise invalid
Date : 2025-07-23 Size : 3kb User : 张安
watch_dog Downloaded：0: Watchdog program design, using verilog HDL language
Date : 2025-07-23 Size : 1kb User : 甄红欣
ROCE_PCI_LED Downloaded：0: verilog project for the communication between PC and PCI board.
Date : 2025-07-23 Size : 1.93mb User : prz
cpu Downloaded：0: 16-bit cpu
Date : 2025-07-23 Size : 3.46mb User : jackielee
test_led Downloaded：0: Verilog language 24-hour counter, digital display, when the key tone on CPLD normal debugging.
Date : 2025-07-23 Size : 821kb User : lgs2007m
I2C Downloaded：0: K2FPGA development board test tutorial- I2C protocol description and verilog read and write I2C devices, Chinese connotation code to verify availability.
Date : 2025-07-23 Size : 1.42mb User : lgs2007m
ADDER_8BIT_FOR_BCD Downloaded：0: Based on the synthesis of two four eight full adder full adder FPGA
Date : 2025-07-23 Size : 420kb User : liu
digital_clock Downloaded：0: Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ctl module, Key_ctl module and Display Module. System goal: 8 LED display time as 9:25:10 displayed as ,09-25-10. (2
Date : 2025-07-23 Size : 1.52mb User : 李龙
yimaqi Downloaded：0: FPGA-based development environment, using 3-8 decoder circuit schematic. Made of a decoder
Date : 2025-07-23 Size : 1kb User : 曌黁

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