VHDL-FPGA-Verilog List Page 823

VHDL-FPGA-Verilog list

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Lab13_mod5cnt Downloaded：0: Module-5 counter is from 0 to 4 repeat count. That is to say, it has to experience 5 state, the output from 000 to 100 and then to 000. Using the Verilog statement in this experiment to describe.
Date : 2025-07-23 Size : 200kb User : penglx1803
Lab14_count3a Downloaded：0: Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
Date : 2025-07-23 Size : 169kb User : penglx1803
Lab15_sw2reg Downloaded：0: Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the registe
Date : 2025-07-23 Size : 171kb User : penglx1803
cores Downloaded：0: a core has been developed for your 32 bit fpu with a least 32x2 input 4 bit operator with round off and 32 bit output and 8 bit exeption data.
Date : 2025-07-23 Size : 25kb User : arka
VHDL Downloaded：0: VHDL modules directly. Points are: to shake, digital display, arbitrary frequency.
Date : 2025-07-23 Size : 6kb User : 滕野
adder4 Downloaded：0: VHDL-based 4-bit adder. One consists of four full adder cascade.
Date : 2025-07-23 Size : 1kb User : 东城
Dlatch3 Downloaded：0: Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
Date : 2025-07-23 Size : 1kb User : 东城
8051corelcd Downloaded：0: on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.
Date : 2025-07-23 Size : 13.03mb User : 陈成
fulladder-using-half-adder Downloaded：0: half adder full adder using half adder in verilog
Date : 2025-07-23 Size : 1kb User : sonumonu
seven-segment-display Downloaded：0: seven segment diaplay
Date : 2025-07-23 Size : 1kb User : sonumonu
alarm_clock Downloaded：0: digital clock with alarm and control
Date : 2025-07-23 Size : 16kb User : sonumonu
cf_fft Downloaded：0: VerilogHDL achieved with 4096-point FFT written algorithm works with quartus
Date : 2025-07-23 Size : 3.12mb User : 毛宏斌

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