VHDL-FPGA-Verilog List Page 825

VHDL-FPGA-Verilog list

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traffic Downloaded：0: Automatic traffic control systems, to design a main, branch roads intersection traffic lights automatically control chip. When the trunk and branch roads requires no vehicle traffic, roads should be kept clear, bright gr
Date : 2025-07-23 Size : 24kb User : 李龙
protect1.3-clpd Downloaded：0: pwm dead zone protection program vhdl minimum pulse width of voice, their own programming, also used in the subject, I hope everyone downloads
Date : 2025-07-23 Size : 13.34mb User : gigi
axi_ad9129 Downloaded：0: AD9129 test source code
Date : 2025-07-23 Size : 2kb User : 木子
ddr2_mem Downloaded：0: DDR2 xilinx top file， you can read or write DDR2 interface。 attention：please control it ！
Date : 2025-07-23 Size : 6kb User : yan
DISPLAY_CONTROL Downloaded：0: Parallel digital control file. This file can be expanded according to their own arbitrary digital tube.
Date : 2025-07-23 Size : 1kb User : 杨空
fasong Downloaded：0: Send orthogonal code files. Can be set to any length and proportion of orthogonal code based on this document.
Date : 2025-07-23 Size : 1kb User : 杨空
helu Downloaded：0: Multiplexing logic signal- digital signal converter. The number of input and output ports can be modified according to this document.
Date : 2025-07-23 Size : 1kb User : 杨空
yanshi_31 Downloaded：0: One signal count delay. Delay time can be modified according to this document.
Date : 2025-07-23 Size : 1kb User : 杨空
turbo_encode Downloaded：1: turbo code encoding proce
Date : 2025-07-23 Size : 6kb User : 周杨兆
VHDL Downloaded：0: Drawing exercises sequential logic circuits, the main test state machine and ASM flowchart
Date : 2025-07-23 Size : 77kb User : lh
ASM Downloaded：0: System design sequential logic circuit description, suitable for most people to learn EDA
Date : 2025-07-23 Size : 330kb User : lh
SZ-VHDL Downloaded：0: System digital logic circuit design methods and introduce examples, analyze good and valuable
Date : 2025-07-23 Size : 3.66mb User : lh

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