VHDL-FPGA-Verilog List Page 822

VHDL-FPGA-Verilog list

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UART Downloaded：0: URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
Date : 2025-07-23 Size : 55kb User : 李龙
altera_cordic-Verilog Downloaded：0: altera_cordic sin cos
Date : 2025-07-23 Size : 1kb User : dan
frm_sync Downloaded：0: This procedure for frame synchronization procedures, using the state machine to prepare the way VHDL description.
Date : 2025-07-23 Size : 1kb User : chenjinhao
sign_det Downloaded：0: This program is a symbol detection VHDL program for detecting the most significant bit of input data symbols.
Date : 2025-07-23 Size : 1kb User : chenjinhao
jpegencode Downloaded：0: verilog source code to realize the encodeing and decodeing for JPEG
Date : 2025-07-23 Size : 173kb User : fengchen
mux16 Downloaded：0: 16* 16-bit multiplier, including simulation files!
Date : 2025-07-23 Size : 117kb User : 望奎
ADPUARTPDPRAM Downloaded：0: ad7606 collected signal data stored in the dual port ram and then sent through the serial port.
Date : 2025-07-23 Size : 6.59mb User : wangyang
AD7606PFSM Downloaded：0: AD7606 using the state machine to simulate timing control samples.
Date : 2025-07-23 Size : 418kb User : wangyang
vhdl-code-for-carwash Downloaded：0: automatic car wash system using verilog hdl where car moves from one state to another state for washing based on time intervel
Date : 2025-07-23 Size : 1kb User : soumith smith
testrom Downloaded：0: My Uploaded Code to test ROM using VHDL.
Date : 2025-07-23 Size : 195kb User : Ali
mux_4 Downloaded：0: Uploaded Source code to design and implementation Multiplexcer using VHDL
Date : 2025-07-23 Size : 112kb User : Ali
Reg_4bit Downloaded：0: Uploaded code to design 4 bit register.
Date : 2025-07-23 Size : 1kb User : Ali

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