VHDL-FPGA-Verilog List Page 831

VHDL-FPGA-Verilog list

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DDS Downloaded：0: DDS signal generator module, using MATLAB to generate a lookup table can output square wave, triangle wave, sawtooth, sine
Date : 2025-07-24 Size : 8.47mb User : 苏杭
8051 Downloaded：0: VHDL language SW8051IP nuclear and add ROM, RAM, RAMX, PLL modules, you can download the HEX file and verify succe
Date : 2025-07-24 Size : 15.48mb User : 苏杭
cdma Downloaded：0: codes for fpga implementation of cdma system using verilog hdl.
Date : 2025-07-24 Size : 3.76mb User : VELAVAN.P
ps2 Downloaded：0: ps2 keyboard driver, you can display the output of the key code on the led
Date : 2025-07-24 Size : 1.84mb User : 交换空
PWM Downloaded：0: Very detailed PWM hardware language program, we hope to help
Date : 2025-07-24 Size : 12.9mb User : 张莱昂
nios_IRQ_verilog Downloaded：0: Interrupt-based hardware platform veriog_nios experiment source code, we hope to help
Date : 2025-07-24 Size : 13.89mb User : 张莱昂
AD Downloaded：0: AD acquisition control timing, control object AD1674 starts and conversion
Date : 2025-07-24 Size : 1kb User : 何小
counter Downloaded：0: Pulse rise or fall along a counting function, and can be configured to initial and trigger conditions
Date : 2025-07-24 Size : 1kb User : 何小
digital_filter Downloaded：0: The data filtering function, can configure the filter width
Date : 2025-07-24 Size : 1kb User : 何小
MS_TMR Downloaded：0: Three modular redundancy design, when a data error, can be automatically corrected
Date : 2025-07-24 Size : 1kb User : 何小
PPS Downloaded：0: The pulse width can be configured with different pulse width, output value
Date : 2025-07-24 Size : 1kb User : 何小
leds Downloaded：0: leds, vhdl spartan 3 nexys2
Date : 2025-07-24 Size : 5kb User : yassinechebbi

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