VHDL-FPGA-Verilog List Page 835

VHDL-FPGA-Verilog list

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SRAM Downloaded：0: Using program SRAM_, speaking, reading and writing tests, first initialized, read and write operations, the inside of the page and bank operation.
Date : 2025-07-24 Size : 527kb User : 王森林
step_on Downloaded：0: Using application state machine control stepping motor, first analysis the smallest step of step motor, and to achieve them. Using SRAM_ program implementation
Date : 2025-07-24 Size : 71kb User : 王森林
ADC_TLC54 Downloaded：0: Using program ADC_TLC549 sampling, digital to analog conversion function implementation, have been debug
Date : 2025-07-24 Size : 486kb User : 王森林
2 Downloaded：0: Computer hardware curriculum design, use QUARTUS II completed the experiment.
Date : 2025-07-24 Size : 318kb User : 1
MIPS-CPU Downloaded：0: Full 32-bit MIPS processor works with the entire project and doc file description
Date : 2025-07-24 Size : 1.79mb User : 何鎏
UART3 Downloaded：0: verilog
Date : 2025-07-24 Size : 1.08mb User : 小杨19900415
multiply_verilog Downloaded：0: Several commonly used multiplier verilog achieve, including ordinary multiplier, multiplier timing, traveling wave multiplier, etc.
Date : 2025-07-24 Size : 3kb User : 杜洵
UART_FIFO Downloaded：0: Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
Date : 2025-07-24 Size : 1.98mb User : zk
carry_skip_adder_verilog Downloaded：0: Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
Date : 2025-07-24 Size : 1kb User : 杜洵
I2C_verilog_bus Downloaded：0: I2C bus is a very common serial bus, it is simple to operate, take up less interface. This procedure describes the method of operation of an EEPROM AT24C02 I2C bus interface, allowing users to learn to read and write I2C
Date : 2025-07-24 Size : 4kb User : 杜洵
FIFO Downloaded：0: Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.
Date : 2025-07-24 Size : 493kb User : zk
RS(204-188)decoder Downloaded：1: rs_decoder.v (top-level document), SyndromeCalc.v (calculating the syndrome), BM_KES.v (BM solving the key equation), Forney.v (Forney algorithm for error samples), CheinSearch.v (search error location), ff_mul.v (
Date : 2025-07-24 Size : 15kb User : 杜洵

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