Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.

UART_FIFO\db\altsyncram_bki1.tdf
.........\..\mux_5oc.tdf
.........\..\prev_cmp_UART_FIFO.asm.qmsg
.........\..\prev_cmp_UART_FIFO.fit.qmsg
.........\..\prev_cmp_UART_FIFO.map.qmsg
.........\..\prev_cmp_UART_FIFO.qmsg
.........\..\prev_cmp_UART_FIFO.sim.qmsg
.........\..\prev_cmp_UART_FIFO.tan.qmsg
.........\..\UART_FIFO.asm.qmsg
.........\..\UART_FIFO.asm_labs.ddb
.........\..\UART_FIFO.cbx.xml
.........\..\UART_FIFO.cmp.bpm
.........\..\UART_FIFO.cmp.cdb
.........\..\UART_FIFO.cmp.ecobp
.........\..\UART_FIFO.cmp.hdb
.........\..\UART_FIFO.cmp.kpt
.........\..\UART_FIFO.cmp.logdb
.........\..\UART_FIFO.cmp.rdb
.........\..\UART_FIFO.cmp.tdb
.........\..\UART_FIFO.cmp0.ddb
.........\..\UART_FIFO.cmp_merge.kpt
.........\..\UART_FIFO.db_info
.........\..\UART_FIFO.eco.cdb
.........\..\UART_FIFO.eds_overflow
.........\..\UART_FIFO.fit.qmsg
.........\..\UART_FIFO.fnsim.cdb
.........\..\UART_FIFO.fnsim.hdb
.........\..\UART_FIFO.fnsim.qmsg
.........\..\UART_FIFO.hier_info
.........\..\UART_FIFO.hif
.........\..\UART_FIFO.lpc.html
.........\..\UART_FIFO.lpc.rdb
.........\..\UART_FIFO.lpc.txt
.........\..\UART_FIFO.map.bpm
.........\..\UART_FIFO.map.cdb
.........\..\UART_FIFO.map.ecobp
.........\..\UART_FIFO.map.hdb
.........\..\UART_FIFO.map.kpt
.........\..\UART_FIFO.map.logdb
.........\..\UART_FIFO.map.qmsg
.........\..\UART_FIFO.map_bb.cdb
.........\..\UART_FIFO.map_bb.hdb
.........\..\UART_FIFO.map_bb.logdb
.........\..\UART_FIFO.pre_map.cdb
.........\..\UART_FIFO.pre_map.hdb
.........\..\UART_FIFO.rpp.qmsg
.........\..\UART_FIFO.rtlv.hdb
.........\..\UART_FIFO.rtlv_sg.cdb
.........\..\UART_FIFO.rtlv_sg_swap.cdb
.........\..\UART_FIFO.sgate.rvd
.........\..\UART_FIFO.sgate_sm.rvd
.........\..\UART_FIFO.sgdiff.cdb
.........\..\UART_FIFO.sgdiff.hdb
.........\..\UART_FIFO.sim.cvwf
.........\..\UART_FIFO.sim.hdb
.........\..\UART_FIFO.sim.qmsg
.........\..\UART_FIFO.sim.rdb
.........\..\UART_FIFO.simfam
.........\..\UART_FIFO.sld_design_entry.sci
.........\..\UART_FIFO.sld_design_entry_dsc.sci
.........\..\UART_FIFO.smp_dump.txt
.........\..\UART_FIFO.syn_hier_info
.........\..\UART_FIFO.tan.qmsg
.........\..\UART_FIFO.tis_db_list.ddb
.........\..\UART_FIFO.tmw_info
.........\..\UART_FIFO_global_asgn_op.abo
.........\..\wed.wsf
.........\FIFO.txt
.........\incremental_db\compiled_partitions\UART_FIFO.root_partition.cmp.atm
.........\..............\...................\UART_FIFO.root_partition.cmp.cfm
.........\..............\...................\UART_FIFO.root_partition.cmp.dfp
.........\..............\...................\UART_FIFO.root_partition.cmp.hdbx
.........\..............\...................\UART_FIFO.root_partition.cmp.kpt
.........\..............\...................\UART_FIFO.root_partition.cmp.logdb
.........\..............\...................\UART_FIFO.root_partition.cmp.rcf
.........\..............\...................\UART_FIFO.root_partition.map.atm
.........\..............\...................\UART_FIFO.root_partition.map.dpi
.........\..............\...................\UART_FIFO.root_partition.map.hdbx
.........\..............\...................\UART_FIFO.root_partition.map.kpt
.........\..............\README
.........\RSR.txt
.........\TSR.txt
.........\UART_FIFO.asm.rpt
.........\UART_FIFO.done
.........\UART_FIFO.fit.rpt
.........\UART_FIFO.fit.smsg
.........\UART_FIFO.fit.summary
.........\UART_FIFO.flow.rpt
.........\UART_FIFO.map.rpt
.........\UART_FIFO.map.summary
.........\UART_FIFO.pin
.........\UART_FIFO.pof
.........\UART_FIFO.qpf
.........\UART_FIFO.qsf
.........\UART_FIFO.qws
.........\UART_FIFO.sim.rpt
.........\UART_FIFO.sof
.........\UART_FIFO.tan.rpt
.........\UART_FIFO.tan.summary
.........\UART_FIFO.vhd

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