Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

MIPS-CPU

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2014-03-20
  • Size : 1.79mb
  • Downloaded :0次
  • Author :何***
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Don't use download software fo downloading.
If download fail,Try it again for free.
Introduction - If you have any usage issues, please Google them yourself
Full 32-bit MIPS processor works with the entire project and doc file description
Packet file list
(Preview for download)


一个完整的MIPS CPU\MIPS\ISE\.untf
..................\....\...\automake.log
..................\....\...\global.xpi
..................\....\...\global_map.ncd
..................\....\...\global_map.ngm
..................\....\...\global_pad.csv
..................\....\...\global_pad.txt
..................\....\...\global_vhdl.prj
..................\....\...\ISE.dhp
..................\....\...\ISE.npl
..................\....\...\main.bld
..................\....\...\main.cmd_log
..................\....\...\main.lso
..................\....\...\main.mrp
..................\....\...\main.nc1
..................\....\...\main.ncd
..................\....\...\main.ngc
..................\....\...\main.ngd
..................\....\...\main.ngm
..................\....\...\main.ngr
..................\....\...\main.pad
..................\....\...\main.pad_txt
..................\....\...\main.par
..................\....\...\main.par_nlf
..................\....\...\main.pcf
..................\....\...\main.placed_ncd_tracker
..................\....\...\main.prj
..................\....\...\main.routed_ncd_tracker
..................\....\...\main.stx
..................\....\...\main.syr
..................\....\...\main.twr
..................\....\...\main.twx
..................\....\...\main.versim_par
..................\....\...\main.xpi
..................\....\...\main_map.ncd
..................\....\...\main_map.ngm
..................\....\...\main_pad.csv
..................\....\...\main_pad.txt
..................\....\...\main_TEST_v_tf.tdo
..................\....\...\main_TEST_v_tf.udo
..................\....\...\main_timesim.nlf
..................\....\...\main_timesim.sdf
..................\....\...\main_timesim.v
..................\....\...\main_vhdl.prj
..................\....\...\TEST.v
..................\....\...\transcript
..................\....\...\vsim.wlf
..................\....\...\work\_info
..................\....\...\xst\work\hdllib.ref
..................\....\...\...\....\vlg0A\Data_Memory.bin
..................\....\...\...\....\...15\global.bin
..................\....\...\...\....\...20\Registers.bin
..................\....\...\...\....\....D\main.bin
..................\....\...\...\....\...30\Decode.bin
..................\....\...\...\....\....B\Code_Memory.bin
..................\....\...\...\....\...41\Control.bin
..................\....\...\...\....\....7\Execute.bin
..................\....\...\...\....\...62\Fetch.bin
..................\....\...\_ngo\netlist.lst
..................\....\...\._projnav\coregen.rsp
..................\....\...\.........\createTF.err
..................\....\...\.........\ednTOngd_tcl.rsp
..................\....\...\.........\global.xst
..................\....\...\.........\ISE.gfl
..................\....\...\.........\ISE_flowplus.gfl
..................\....\...\.........\main.xst
..................\....\...\.........\map.log
..................\....\...\.........\nc1TOncd_tcl.rsp
..................\....\...\.........\netgen_par_tcl.rsp
..................\....\...\.........\par.log
..................\....\...\.........\posttrc.log
..................\....\...\.........\runXst_tcl.rsp
..................\....\...\__projnav.log
..................\....\mips.doc
..................\....\ModelSim\MIPS.cr.mti
..................\....\........\MIPS.mpf
..................\....\........\work\@code_@memory\verilog.asm
..................\....\........\....\.............\_primary.dat
..................\....\........\....\.............\_primary.vhd
..................\....\........\....\...ntrol\verilog.asm
..................\....\........\....\........\_primary.dat
..................\....\........\....\........\_primary.vhd
..................\....\........\....\.data_@memory\verilog.asm
..................\....\........\....\.............\_primary.dat
..................\....\........\....\.............\_primary.vhd
..................\....\........\....\..ecode\verilog.asm
..................\....\........\....\.......\_primary.dat
..................\....\........\....\.......\_primary.vhd
..............
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is one of the largest source code repositories on the Internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.