VHDL-FPGA-Verilog List Page 834

VHDL-FPGA-Verilog list

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conv_encode Downloaded：0: The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by contrast matlab and modelsim simulation results valida
Date : 2025-07-24 Size : 18.69mb User : 郭婷
fpgahdl_xilinx-edk.tar Downloaded：0: xilinx zynq 7000 FPGA demo
Date : 2025-07-24 Size : 15.85mb User : xujin2002ji
fpga-nois Downloaded：0: Which contains the four noic nuclear fpga verilog (i2c, rs232, can, 8051). Tested good
Date : 2025-07-24 Size : 8.74mb User : feixue
fir_verilog_matlab Downloaded：0: This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.
Date : 2025-07-24 Size : 1.29mb User : 郭婷
FPGA_Uart Downloaded：0: FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main reference serial transmission program. This program written
Date : 2025-07-24 Size : 661kb User : suchenguang
FPGA_cymometer Downloaded：0: FPGA procedures, verilog HDL language, provides a way to achieve a frequency meter, development environment for Quartus ii 13.0, beginner verilog HDL language students can refer to the next
Date : 2025-07-24 Size : 3.39mb User : suchenguang
digitalvoltemterdesign Downloaded：0: FPGA on the digital voltmeter design source code, has been proven feasible
Date : 2025-07-24 Size : 10kb User : 田
fifo_csm Downloaded：0: first in first out
Date : 2025-07-24 Size : 1kb User : markt
NiosIISPI Downloaded：0: NiosII on spi bus design, source code easier to understand, to help learners understand and transplantation
Date : 2025-07-24 Size : 15.3mb User : 田
I2C_control Downloaded：0: Two-wire I2C serial bus control terminal verilog source code, after compiling and modelsim simulation is correct!
Date : 2025-07-24 Size : 93kb User : 林伟建
music Downloaded：0: Play with verilog routines buzzer music, music Zhiailisi
Date : 2025-07-24 Size : 597kb User : 哈工程贾硕
CT74125 Downloaded：0: A four-bus buffer design, pro-test so. Suitable for beginners. FPGA Development
Date : 2025-07-24 Size : 300kb User : 哈工程贾硕

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