FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main reference serial transmission program. This program written using quartus ii 13.0.

uart\ClkDivToPuls.v
....\ClkDivToSquareWave.v
....\db\logic_util_heursitic.dat
....\..\prev_cmp_uart.qmsg
....\..\uart.asm.qmsg
....\..\uart.asm.rdb
....\..\uart.cbx.xml
....\..\uart.cmp.bpm
....\..\uart.cmp.cdb
....\..\uart.cmp.hdb
....\..\uart.cmp.idb
....\..\uart.cmp.kpt
....\..\uart.cmp.logdb
....\..\uart.cmp.rdb
....\..\uart.cmp0.ddb
....\..\uart.cmp_merge.kpt
....\..\uart.db_info
....\..\uart.fit.qmsg
....\..\uart.hier_info
....\..\uart.hif
....\..\uart.ipinfo
....\..\uart.lpc.html
....\..\uart.lpc.rdb
....\..\uart.lpc.txt
....\..\uart.map.ammdb
....\..\uart.map.bpm
....\..\uart.map.cdb
....\..\uart.map.hdb
....\..\uart.map.kpt
....\..\uart.map.logdb
....\..\uart.map.qmsg
....\..\uart.map.rdb
....\..\uart.map_bb.cdb
....\..\uart.map_bb.hdb
....\..\uart.map_bb.logdb
....\..\uart.pplq.rdb
....\..\uart.pre_map.hdb
....\..\uart.pti_db_list.ddb
....\..\uart.root_partition.map.reg_db.cdb
....\..\uart.routing.rdb
....\..\uart.rtlv.hdb
....\..\uart.rtlv_sg.cdb
....\..\uart.rtlv_sg_swap.cdb
....\..\uart.sgdiff.cdb
....\..\uart.sgdiff.hdb
....\..\uart.sld_design_entry.sci
....\..\uart.sld_design_entry_dsc.sci
....\..\uart.smart_action.txt
....\..\uart.smp_dump.txt
....\..\uart.sta.qmsg
....\..\uart.sta.rdb
....\..\uart.sta_cmp.8_slow.tdb
....\..\uart.syn_hier_info
....\..\uart.tis_db_list.ddb
....\..\uart.tmw_info
....\..\uart.vpr.ammdb
....\Display4Num.v
....\EdgeChk.v
....\incremental_db\compiled_partitions\uart.db_info
....\..............\...................\uart.root_partition.cmp.ammdb
....\..............\...................\uart.root_partition.cmp.cdb
....\..............\...................\uart.root_partition.cmp.dfp
....\..............\...................\uart.root_partition.cmp.hdb
....\..............\...................\uart.root_partition.cmp.kpt
....\..............\...................\uart.root_partition.cmp.logdb
....\..............\...................\uart.root_partition.cmp.rcfdb
....\..............\...................\uart.root_partition.map.cdb
....\..............\...................\uart.root_partition.map.dpi
....\..............\...................\uart.root_partition.map.hbdb.cdb
....\..............\...................\uart.root_partition.map.hbdb.hb_info
....\..............\...................\uart.root_partition.map.hbdb.hdb
....\..............\...................\uart.root_partition.map.hbdb.sig
....\..............\...................\uart.root_partition.map.hdb
....\..............\...................\uart.root_partition.map.kpt
....\..............\README
....\LedDisplay.v
....\output_files\uart.asm.rpt
....\............\uart.cdf
....\............\uart.done
....\............\uart.fit.rpt
....\............\uart.fit.smsg
....\............\uart.fit.summary
....\............\uart.flow.rpt
....\............\uart.jdi
....\............\uart.map.rpt
....\............\uart.map.summary
....\............\uart.pin
....\............\uart.pof
....\............\uart.sof
....\............\uart.sta.rpt
....\............\uart.sta.summary
....\top.v
....\top.v.bak
....\uart.qpf
....\uart.qsf
....\uart.qws
....\UartRec.v
....\UartRec.v.bak
....\UartSend.v
....\UartSend.v.bak

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