VHDL-FPGA-Verilog List Page 748

VHDL-FPGA-Verilog list

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PCI_IF_AMCC-S5920.ZIP Downloaded：0: Design for PCI IF AMCC S5920
Date : 2025-06-30 Size : 2kb User : Victor Rogov
ADDA_2C5 Downloaded：0: AD and DA conversion, it is a good learning routines for learners
Date : 2025-06-30 Size : 3.92mb User : 李晶
fs_re Downloaded：0: Ultrasonic pulse transmission and timing program，pulse sequence number and cycle can be set up
Date : 2025-06-30 Size : 665kb User : 李晶
FPGA_CRC Downloaded：0: Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source code, and the principles of my hand calculations. This program has been ModelSim-Altera simul
Date : 2025-06-30 Size : 1.14mb User : yuantielei
ModelSim-Settings Downloaded：0: Set ModelSim simulation steps, using Quartus II 13.0 (32-bit) University Program VWF programming function waveform file, use the ModelSim-Altera simulation.
Date : 2025-06-30 Size : 377kb User : yuantielei
Middlefilter Downloaded：0: FPGA-based middle filter using verilog language, simulation results properly.
Date : 2025-06-30 Size : 68kb User : luotian
clock Downloaded：0: Digital clock LCD1602 display can be corrected. Compilation environment QUARTUS II 7.2
Date : 2025-06-30 Size : 2.06mb User : zjh
LCD1602-DRIVER(vhdl) Downloaded：0: LCD602 drive module source code Can be used directly Compilation environment QUARTUS II 7.2
Date : 2025-06-30 Size : 331kb User : zjh
Experiment-of-FPGA_DE2 Downloaded：0: Experiment of FPGA_DE2
Date : 2025-06-30 Size : 1.29mb User : 范萍
sp605_BRD_rdf0033_13.3_c Downloaded：0: SP605 SFP test code
Date : 2025-06-30 Size : 5.62mb User : genghelong
ahb_slave_ssrw Downloaded：0: submodule used for simple configuration register/RAM accesses ssrw stands for simple single read write.
Date : 2025-06-30 Size : 2kb User : genghelong
Verilog-Digital-control Downloaded：0: Verilog HDL digital control system design implementation- Xian Jin- source code-4469
Date : 2025-06-30 Size : 11.25mb User : genghelong

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