FPGA-based middle filter using verilog language, simulation results properly.

pxq67\pxq.cr.mti
.....\pxq.mpf
.....\pxq.v
.....\pxq.v.bak
.....\pxq_tb.v
.....\pxq_tb.v.bak
.....\vsim.wlf
.....\work\@_opt\vopt3g2n7c
.....\....\.....\vopt70rj7c
.....\....\.....\vopt7ezm7a
.....\....\.....\voptagdf7c
.....\....\.....\voptbyki7a
.....\....\.....\voptee2cdc
.....\....\.....\voptidy98a
.....\....\.....\voptm6k65a
.....\....\.....\voptmad3zb
.....\....\.....\voptr8205c
.....\....\.....\vopts322nc
.....\....\.....\voptw1qzvc
.....\....\.....\voptwvhw3e
.....\....\.....\_deps
.....\....\.....1\vopt146iry
.....\....\......\vopt46wfiy
.....\....\......\vopt916797
.....\....\......\voptdhv497
.....\....\......\voptdi7hkb
.....\....\......\voptg1h197
.....\....\......\voptihf0zy
.....\....\......\voptkt6x57
.....\....\......\voptn15wyy
.....\....\......\voptshtsyy
.....\....\......\voptvigk37
.....\....\......\voptxagnvy
.....\....\......\voptykxhx9
.....\....\......\_deps
.....\....\.....2\vopt0936k3
.....\....\......\vopt4sr3k3
.....\....\......\vopt70fxw2
.....\....\......\vopt8ve0e3
.....\....\......\voptbg4tw2
.....\....\......\voptbk4wa3
.....\....\......\vopte0tnw2
.....\....\......\voptfe1sw0
.....\....\......\vopti59nf5
.....\....\......\voptisfjs2
.....\....\......\voptnw3g83
.....\....\......\voptsmsd53
.....\....\......\voptxrd9k3
.....\....\......\_deps
.....\....\paixu\_primary.dat
.....\....\.....\_primary.dbs
.....\....\.....\_primary.vhd
.....\....\....._test\_primary.dat
.....\....\..........\_primary.dbs
.....\....\..........\_primary.vhd
.....\....\_info
.....\....\.temp\vlog3yv5h5
.....\....\.....\vlogc5ayqy
.....\....\.....\vlogh7brdt
.....\....\_vmake
.....\....\@_opt
.....\....\@_opt1
.....\....\@_opt2
.....\....\paixu
.....\....\paixu_test
.....\....\_temp
.....\work
pxq67

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