VHDL-FPGA-Verilog List Page 744

VHDL-FPGA-Verilog list

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rtl Downloaded：0: Pll controlled by FPGA on changing PLL Output frequency. Interface spi interface.
Date : 2025-06-30 Size : 57kb User : wanzhuan
crc Downloaded：0: An alternative way to generate crc, changing the water first structure to use parallel structures. To develop ideas.
Date : 2025-06-30 Size : 3.72mb User : wanzhuan
special_crcb Downloaded：0: An alternative way to generate crc, changing the water first structure to use parallel structures. To develop ideas.
Date : 2025-06-30 Size : 3.72mb User : wanzhuan
a Downloaded：0: Decimal counter vhdl fpga-based, easy to use
Date : 2025-06-30 Size : 738kb User : li
hengwenxiang Downloaded：0: Thermostat controller, controlled by a state machine connected to the temperature sensors, temperature control. The code is written in verilog thermostat control, after each statement has a Chinese description
Date : 2025-06-30 Size : 1kb User : 刘禹韬
clock Downloaded：0: There are double anti-shake digital clock module, minutes and seconds can be achieved when the regulation, 24-hour clock.
Date : 2025-06-30 Size : 2kb User : 刘禹韬
8bit_multiplier Downloaded：0: Unsigned 8bit serial multiplier, the state machine implementation, realized by adding the shift multiplication function.
Date : 2025-06-30 Size : 1kb User : 刘禹韬
syn_fifo_style_1 Downloaded：0: verilog achieve, asynchronous FIFO. All code in a module.
Date : 2025-06-30 Size : 1kb User : 刘禹韬
syn_fifo_style_2 Downloaded：0: Verilog achieved by the asynchronous FIFO, divided into multiple modules.
Date : 2025-06-30 Size : 1kb User : 刘禹韬
mcs51 Downloaded：0: A simple communication with the microcontroller 51 programs, simulation has been passed!
Date : 2025-06-30 Size : 1kb User : lilei
ASBoard_restored Downloaded：0: AD acquisition procedures, do their own, SPI communication protocol, multi-channel acquisition
Date : 2025-06-30 Size : 5.82mb User : 陈照
shift_1x64_vhd Downloaded：0: register shifter of 64bits
Date : 2025-06-30 Size : 1kb User : anas

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