Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source code, and the principles of my hand calculations. This program has been ModelSim-Altera simulation, simulation waveform files are in this document.

FPGA_CRC\CCITT.qpf
........\CCITT.qsf
........\CCITT.qws
........\CCITT.v
........\CCITT.v.bak
........\CCITT_nativelink_simulation.rpt
........\db\CCITT.asm.qmsg
........\..\CCITT.asm.rdb
........\..\CCITT.asm_labs.ddb
........\..\CCITT.cbx.xml
........\..\CCITT.cmp.cdb
........\..\CCITT.cmp.hdb
........\..\CCITT.cmp.idb
........\..\CCITT.cmp.kpt
........\..\CCITT.cmp.logdb
........\..\CCITT.cmp.rdb
........\..\CCITT.cmp0.ddb
........\..\CCITT.cmp2.ddb
........\..\CCITT.cmp_merge.kpt
........\..\CCITT.db_info
........\..\CCITT.eda.qmsg
........\..\CCITT.fit.qmsg
........\..\CCITT.hier_info
........\..\CCITT.hif
........\..\CCITT.ipinfo
........\..\CCITT.lpc.html
........\..\CCITT.lpc.rdb
........\..\CCITT.lpc.txt
........\..\CCITT.map.ammdb
........\..\CCITT.map.cdb
........\..\CCITT.map.hdb
........\..\CCITT.map.kpt
........\..\CCITT.map.logdb
........\..\CCITT.map.qmsg
........\..\CCITT.map.rdb
........\..\CCITT.pre_map.hdb
........\..\CCITT.pti_db_list.ddb
........\..\CCITT.root_partition.map.reg_db.cdb
........\..\CCITT.routing.rdb
........\..\CCITT.rtlv.hdb
........\..\CCITT.rtlv_sg.cdb
........\..\CCITT.rtlv_sg_swap.cdb
........\..\CCITT.sgdiff.cdb
........\..\CCITT.sgdiff.hdb
........\..\CCITT.sld_design_entry.sci
........\..\CCITT.sld_design_entry_dsc.sci
........\..\CCITT.smart_action.txt
........\..\CCITT.sta.qmsg
........\..\CCITT.sta.rdb
........\..\CCITT.sta_cmp.5_slow.tdb
........\..\CCITT.syn_hier_info
........\..\CCITT.tis_db_list.ddb
........\..\CCITT.vpr.ammdb
........\..\logic_util_heursitic.dat
........\..\prev_cmp_CCITT.qmsg
........\incremental_db\compiled_partitions\CCITT.db_info
........\..............\...................\CCITT.root_partition.cmp.ammdb
........\..............\...................\CCITT.root_partition.cmp.cdb
........\..............\...................\CCITT.root_partition.cmp.dfp
........\..............\...................\CCITT.root_partition.cmp.hdb
........\..............\...................\CCITT.root_partition.cmp.kpt
........\..............\...................\CCITT.root_partition.cmp.logdb
........\..............\...................\CCITT.root_partition.cmp.rcfdb
........\..............\...................\CCITT.root_partition.map.cdb
........\..............\...................\CCITT.root_partition.map.dpi
........\..............\...................\CCITT.root_partition.map.hbdb.cdb
........\..............\...................\CCITT.root_partition.map.hbdb.hb_info
........\..............\...................\CCITT.root_partition.map.hbdb.hdb
........\..............\...................\CCITT.root_partition.map.hbdb.sig
........\..............\...................\CCITT.root_partition.map.hdb
........\..............\...................\CCITT.root_partition.map.kpt
........\..............\README
........\output_files\CCITT.asm.rpt
........\............\CCITT.done
........\............\CCITT.eda.rpt
........\............\CCITT.fit.rpt
........\............\CCITT.fit.smsg
........\............\CCITT.fit.summary
........\............\CCITT.flow.rpt
........\............\CCITT.jdi
........\............\CCITT.map.rpt
........\............\CCITT.map.summary
........\............\CCITT.pin
........\............\CCITT.pof
........\............\CCITT.sof
........\............\CCITT.sta.rpt
........\............\CCITT.sta.summary
........\simulation\modelsim\CCITT.sft
........\..........\........\CCITT.vo
........\..........\........\CCITT.vt
........\..........\........\CCITT_fast.vo
........\..........\........\CCITT_modelsim.xrf
........\..........\........\CCITT_run_msim_gate_verilog.do
........\..........\........\CCITT_run_msim_rtl_verilog.do
........\..........\........\CCITT_run_msim_rtl_verilog.do.bak
........\..........\........\CCITT_run_msim_rtl_verilog.do.bak1
........\..........\........\CCITT_run_msim_rtl_verilog.do.bak10
........\..........\........\CCITT_run_msim_rtl_verilog.do.bak11
........\..........\........\CCITT_run_msim_rtl_verilog.do.bak2
........\..........\........\CCITT_run_msim_rtl_verilog.do.bak3

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．