VHDL-FPGA-Verilog List Page 750

VHDL-FPGA-Verilog list

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state Downloaded：0: Detection of the input sequence to achieve 1. Low asynchronous reset 2. Detection sequence is characterized by 10010 3. High output, maintaining a clock cycle 4. Data sequence data for one clock cycle as a state, a risin
Date : 2025-06-30 Size : 1kb User : 沈骞
trafficlight Downloaded：0: traffic light
Date : 2025-06-30 Size : 335kb User : 曾德天
AD9850 Downloaded：0: DDS chip AD9850 ARM controller code
Date : 2025-06-30 Size : 2.5mb User : liam
DE2_115_Audio Downloaded：0: DE2_115 pfga finish Audio test
Date : 2025-06-30 Size : 1.82mb User : lzc
DE3_340_USB Downloaded：0: de3 fpga finish the sd test
Date : 2025-06-30 Size : 4.21mb User : lzc
cnt30 Downloaded：0: The realization of certain countdown function, then the use of digital tube display the corresponding number, until all the numbers all 0
Date : 2025-06-30 Size : 217kb User : 白雪松
S2_div Downloaded：0: 1, this routine is to practice clock divider, you can watch the simulation waveform 2, are interested can be added to the hardware logic analyzer waveform viewing
Date : 2025-06-30 Size : 3.05mb User : 可难
xianshi Downloaded：0: Digital logic circuits display
Date : 2025-06-30 Size : 1kb User : 许
div50m Downloaded：0: 50M divider, the microcontroller can target different frequencies, modification factor to achieve different divider
Date : 2025-06-30 Size : 1kb User : 许
dianzhen Downloaded：0: Animation matrix scans can switch between the different states.
Date : 2025-06-30 Size : 2kb User : 许
nn_pid Downloaded：0: This a bp neural network controller for aircraft control system+PID VHDL program, which the module is not complete, but generally module has great reference significance
Date : 2025-06-30 Size : 607kb User : 王力
fujitsuPR_FINAL Downloaded：0: OMNIVISION DEMONSTRATES LATEST OMNIBSI 8MEGAPIXEL SOLUTION AT MOBILE WORLD CONGRE
Date : 2025-06-30 Size : 27kb User : 张五

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