VHDL-FPGA-Verilog List Page 650

VHDL-FPGA-Verilog list

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3jiekaihuanDAFIR Downloaded：0: Open-loop DNA FIR filter, can improve the speed of the filter, the procedure for the three coefficients, open-ring form four inputs DA FIR filter.
Date : 2025-06-26 Size : 1kb User : yang
iir_pipe Downloaded：0: The procedure applied to the pipeline techniques to achieve an IIR filter, which consists of a non-recursive portion and having a delay of 2 and a coefficient of the recursive part 9/16 constituted.
Date : 2025-06-26 Size : 1kb User : yang
duoxiangchouqu Downloaded：0: The program uses polyphase decomposition way to achieve the decimation filter, the speed of the extractor runs faster than the down sampler of the FIR filter is generally faster R times.
Date : 2025-06-26 Size : 1kb User : yang
sinclvboqi Downloaded：0: The program implements a sinc filter fractional delay rate converter, where R = 0.75.
Date : 2025-06-26 Size : 1kb User : yang
farrow Downloaded：0: The program polynomial fractional delay (farrow) design.
Date : 2025-06-26 Size : 1kb User : yang
Mini-Risc-core Downloaded：0: This a Mini-RISC CPU/Microcontroller that is mostly compatible with the PIC 16C57 Microchip.
Date : 2025-06-26 Size : 101kb User : 金铁男
Low-Power-FIR-Filter Downloaded：0: This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
Date : 2025-06-26 Size : 427kb User : 金铁男
DES_Triple-DES-IP-Cores Downloaded：0: Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
Date : 2025-06-26 Size : 69kb User : 金铁男
PS2_SOC1 Downloaded：0: This a state-machine driven serial-to-parallel and parallel-to-serial interface to the ps2 style keyboard interface.
Date : 2025-06-26 Size : 81kb User : 金铁男
PS2_SOC2 Downloaded：0: This a state-machine driven serial-to-parallel and parallel-to-serial interface to the ps2 style mouse.
Date : 2025-06-26 Size : 26kb User : 金铁男
LIBRARY-IEEE Downloaded：0: Converting the frequency signal into a frequency of 29hz of 1Mhz. Divider
Date : 2025-06-26 Size : 3kb User : 何三
DDS Downloaded：0: dds test program, for example, can issue of the DDS frequency and phase controlled sinusoidal
Date : 2025-06-26 Size : 1kb User : ggww

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