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VHDL-FPGA-Verilog list
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To implement a traffic light in verilog.The experiment of SMIE
Date : 2025-06-26 Size : 468kb User : Wangchy

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An implementation in verilog on Mealy FSM
Date : 2025-06-26 Size : 471kb User : Wangchy

cycloneIII_3c120_dev_niosII_standard is atlter official routine
Date : 2025-06-26 Size : 1.57mb User : zfy

cycloneIII_3c120_dev_power_demo atlera company official routines
Date : 2025-06-26 Size : 2.02mb User : zfy

cycloneIII_3c120_dev_my_first_fpga altera official routines
Date : 2025-06-26 Size : 973kb User : zfy

cycloneIII_3c120_dev_quartus_pinouts altera official source
Date : 2025-06-26 Size : 19kb User : zfy

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Electronic watch has the basic function of the display and adjust, can display when, minutes, seconds, and milliseconds, and through the keys work mode selection, working mode, there are four, respectively is normal timi
Date : 2025-06-26 Size : 3kb User : 刘亮

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Based on the principle of altera cyclone Ⅳ EP4CE30F23C8N DDS, design programs and source code. Can be directly admitted to the development board, containing modelsim waveform, easy to use simulation
Date : 2025-06-26 Size : 6.97mb User : 汪书潮

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Altera cyclone Ⅳ EP4CE30F23C8N based platform. Includes sync structure fifo2 principle, design and source code. Can be directly admitted to the development board, containing modelsim waveform, easy to use simulation
Date : 2025-06-26 Size : 4.22mb User : 汪书潮

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ad9708 and ad9280 programs, ad collection come again da output, in the middle of some of the algorithms can add their own.
Date : 2025-06-26 Size : 6.04mb User :

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Stepper motor, in fact, I do not know why this is, and just want to download a code, a lot of understanding
Date : 2025-06-26 Size : 11kb User : 周伟

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adc0804 8-bit DAC, high portability in the FPGA
Date : 2025-06-26 Size : 493kb User : 张国成
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