VHDL-FPGA-Verilog List Page 643

VHDL-FPGA-Verilog list

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double_closed_loop Downloaded：0: based on zynq_7000 fpga-MOTOR CONTROL
Date : 2025-06-26 Size : 193kb User : 葛明明
RS-encoder Downloaded：0: RSC encoder in VHDL. Hope it helpful.
Date : 2025-06-26 Size : 4kb User : thang
V2.tar Downloaded：2: SDIO slave, written in verilog, does not support SPI mode.
Date : 2025-06-26 Size : 9kb User : corgano
APB_slave Downloaded：0: APB slave template for AMBA bus written in Verilog
Date : 2025-06-26 Size : 1kb User : corgano
or1200.tar Downloaded：0: OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
Date : 2025-06-26 Size : 3.52mb User : corgano
verilog-arbiter.tar Downloaded：0: Verilog arbitrator for Wishbone R3 compliant bus
Date : 2025-06-26 Size : 5kb User : corgano
wb_sdram_ctrl.tar Downloaded：0: Generic Wishbone R3 compliant SDRAM controller written in Verilog
Date : 2025-06-26 Size : 10kb User : corgano
bt656_to_yuv422 Downloaded：1: bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal
Date : 2025-06-26 Size : 1kb User : zbunix
bt656_timing_analysis Downloaded：0: The video standard ITU-R.656 timing analysis
Date : 2025-06-26 Size : 81kb User : zbunix
Basys2Lcd Downloaded：0: This the file of controling a LCD display of Basys2 board used to pass the exams of VHDL
Date : 2025-06-26 Size : 1kb User : plaukuotis
pingpong Downloaded：0: Use Verilog HDL to achieve a table tennis game, and through the verification on the DE2 development board.
Date : 2025-06-26 Size : 1.72mb User : 杨震
fpga-usb-verilog-test Downloaded：0: Red hurricane development board of the USB test source code, including documentation, FPGA verilog code, cy68013 firmware program, PC test program. Realization of USB loopback test, which can be taken as reference to the
Date : 2025-06-26 Size : 15.16mb User : 贾程序

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