VHDL-FPGA-Verilog List Page 655

VHDL-FPGA-Verilog list

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arbitrator Downloaded：0: arbitrator for network on chip
Date : 2025-06-26 Size : 821kb User : shyam s
AD5300 Downloaded：0: The FPGA external AD code, the FPGA chip using xilinx sptan3e can realize the collection of the AD
Date : 2025-06-26 Size : 1kb User : chenkun
PS2 Downloaded：0: The FPGA external PS2j keyboard part of the code, the FPGA chip using xilinx sptan3e can realize the keyboard and a serial port communication
Date : 2025-06-26 Size : 1kb User : chenkun
Rxd-new Downloaded：0: FPGA serial sections to send code, the FPGA chip using xilinx sptan3e can implement on FPGA and computer communications
Date : 2025-06-26 Size : 1kb User : chenkun
SPI Downloaded：0: FPGA SPI part of the code, the FPGA chip using xilinx sptan3e can realize SPI communication, FPGA is used to control the external 74hc595 are ne
Date : 2025-06-26 Size : 2kb User : chenkun
TXd_FIFO Downloaded：0: The FPGA to send part of the code, serial communication, the FPGA chip using xilinx sptan3e can implement on FPGA send through max232 computer data
Date : 2025-06-26 Size : 1kb User : chenkun
key Downloaded：0: Achieve FPGA button control part of the code, the FPGA chip using xilinx sptan3e can realize after press the button the FPGA through max232 send data to a computer
Date : 2025-06-26 Size : 1kb User : chenkun
serial-ports2 Downloaded：0: 12bit parallel to serial decoder and aynthesis result
Date : 2025-06-26 Size : 614kb User : eric
second Downloaded：0: Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design, and simulation waveform, and there is a corresponding report. The report also includes a BC
Date : 2025-06-26 Size : 455kb User : 文闯
RISC_SPM Downloaded：0: it s an 8 bit risc alu.
Date : 2025-06-26 Size : 121kb User : liu
lab1_multicycle_dds Downloaded：0: Generate more than one cycle of the signal direct digital synthesizer Verilog code, has been tested symbol require spectral purity of the signal generated in matlab
Date : 2025-06-26 Size : 3.18mb User : 林森
start_lab4 Downloaded：0: Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
Date : 2025-06-26 Size : 21.16mb User : 林森

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