VHDL-FPGA-Verilog List Page 656

VHDL-FPGA-Verilog list

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wcdma.v Downloaded：0: Example 13-6 FPGA design of wireless communication source code, FPGA implementation of WCDMA system cell search
Date : 2025-06-26 Size : 5kb User : xuweiwei
MultCIC Downloaded：0: Three integral CIC comb filter FPGA implementation code, including the integration module, extraction module and a comb and a top-level module module implementation code
Date : 2025-06-26 Size : 3.32mb User : xuweiwei
MultHalfBand Downloaded：1: Multi-level half-band filter FPGA, using six filters for sampling frequencies 50Hz down to 3200Hz extraction system for the front five and a half-band filter, the last stage of the ordinary FIR filter
Date : 2025-06-26 Size : 1.44mb User : xuweiwei
modulation-and-demodulation Downloaded：1: FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM m
Date : 2025-06-26 Size : 5kb User : xuweiwei
VHDL-clock Downloaded：0: Written in VHDL,the digital clock procedures can display every minute, the time can be adjusted, but also to set the alarm
Date : 2025-06-26 Size : 1.39mb User : Brriot
Bucket-shift-register Downloaded：0: Bucket shift register.The main realization of cyclic shift function.Single module, help to transplant, and easy to use personnel to quickly understand and apply
Date : 2025-06-26 Size : 442kb User : august
dtsmg Downloaded：0: Real-time display and application of dynamic digital tube, primarily to implement a simple no control bits when every minute digital clock six digital realization of the first two hours three or four minute display displ
Date : 2025-06-26 Size : 6.47mb User : 宋文儒
09_uart2 Downloaded：0: FPGA UART
Date : 2025-06-26 Size : 103kb User : 陈辉
vhdl Downloaded：0: vhdl code for internet interface
Date : 2025-06-26 Size : 11kb User : original_zomby
dspbuilder Downloaded：0: ALTERA DSP-BUILDER TO DEVELOP PROJECT
Date : 2025-06-26 Size : 3.23mb User : xiang yao
PCIdataout Downloaded：0: C program containing the data to be sent and Verlog program
Date : 2025-06-26 Size : 5.44mb User : YAN
ug947-vivado-partial-reconfiguration-tutorial(1). Downloaded：0: tcl partial reconfig synthesis code
Date : 2025-06-26 Size : 59kb User : shyam s

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