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VHDL-FPGA-Verilog list
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VERILOG language environment of the LTM display development encapsulated module.
Date : 2025-06-26 Size : 2.74mb User : 王星

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use usb to send data to computer
Date : 2025-06-26 Size : 3.47mb User : 刘阳

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his program is based on the Quartus II, and when through digital display hours, minutes, seconds, and has an alarm clock function, button through school.
Date : 2025-06-26 Size : 1kb User : jinsan

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cymometer implementation, involving 10 times divider, generating gate controling signal and frequency measurement
Date : 2025-06-26 Size : 2kb User : s

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Own implements a simple no parity UART protocol. altera EP4C6E verification
Date : 2025-06-26 Size : 5.86mb User : yanzeyu

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Use verilog HDL to achieve full adder function
Date : 2025-06-26 Size : 26kb User : 知多少

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sample program for up3 education kit
Date : 2025-06-26 Size : 2kb User : pepan

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verilog 8 bit cpu working condition but need minor modification
Date : 2025-06-26 Size : 10kb User : shobhit

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picoblaze example , very good working tutorial
Date : 2025-06-26 Size : 17kb User : shobhit

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LVDS ADC AD9289 FPGA reference design
Date : 2025-06-26 Size : 1.25mb User : Eddie

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Programming on the signal modulation in FPGA, which includes ASK, FSK, encoder and decoder of CMI
Date : 2025-06-26 Size : 640kb User : glywhh

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Here contains design wireless communication FPGA this book in all Matlab and Verilog code
Date : 2025-06-26 Size : 176kb User : glywhh
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