VHDL-FPGA-Verilog List Page 388

VHDL-FPGA-Verilog list

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LCD126484 Downloaded：0: about 12864
Date : 2025-06-11 Size : 73kb User : renlulu
swfsm Downloaded：0: the finite state machine vhdl code for the simple stopwatch file
Date : 2025-06-11 Size : 2kb User : Echo Li
segsweep Downloaded：0: VHDL seg
Date : 2025-06-11 Size : 194kb User : jack
traffic_lights Downloaded：0: Using Verilog HDL programming language, to achieve the crossroads of traffic lights function, can be simulated in FPGA hardware on (the default hardware crystal is 50MHz).
Date : 2025-06-11 Size : 3kb User : krj
rom_255 Downloaded：0: By controlling the keyboard or by 50MHz crystal occur long after the division to change every second step, through the 8-bit parallel digital output signal, and the digital signal after decoding circuit tube output promp
Date : 2025-06-11 Size : 1.29mb User : maomaoyu
mux_2to1 Downloaded：0: Data selector 2-to-1 that is, when x = 1, the output m = y when s = 0, the output m = x.
Date : 2025-06-11 Size : 245kb User : maomaoyu
char_7seg Downloaded：0: Seven-segment LED display simple characters, 0-9 digital loop display four characters
Date : 2025-06-11 Size : 256kb User : maomaoyu
bcd_add_1bit Downloaded：0: BCD code to binary code conversion of a BCD adder two BCD adder
Date : 2025-06-11 Size : 223kb User : maomaoyu
baseonFPGAclock Downloaded：0: verilog language, implemented on the FPGA alarm clock, calendar, time display, stopwatch in one of the electronic clock and calendar. Can be displayed on LCD
Date : 2025-06-11 Size : 153kb User : fmxonfei
AD9826-verilog Downloaded：1: the module of ad9826 with verilog
Date : 2025-06-11 Size : 5kb User : zengshaoqing
ADP5052.PDF Downloaded：0: Multiple regulated output voltage can be configured very suitable for fpga power
Date : 2025-06-11 Size : 1018kb User : 王子文
mux_16bit_sign Downloaded：0: 16-bit signed and unsigned multiplier FPGA source code
Date : 2025-06-11 Size : 5kb User : john

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